| /linux-6.1.9/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gmu.c | 17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
24 gmu->hung = true; in a6xx_gmu_fault()
35 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
38 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
39 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
42 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
44 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
48 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
51 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
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| D | a6xx_hfi.c | 26 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
57 if (!gmu->legacy) in a6xx_hfi_queue_read()
64 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
88 if (!gmu->legacy) { in a6xx_hfi_queue_write()
96 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
100 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack() argument
103 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
108 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_ack()
112 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
119 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, in a6xx_hfi_wait_for_ack()
[all …]
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| D | a6xx_gmu.h | 94 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) in gmu_read() argument
96 return msm_readl(gmu->mmio + (offset << 2)); in gmu_read()
99 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) in gmu_write() argument
101 msm_writel(value, gmu->mmio + (offset << 2)); in gmu_write()
105 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) in gmu_write_bulk() argument
107 memcpy_toio(gmu->mmio + (offset << 2), data, size); in gmu_write_bulk()
111 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) in gmu_rmw() argument
113 u32 val = gmu_read(gmu, reg); in gmu_rmw()
117 gmu_write(gmu, reg, val | or); in gmu_rmw()
120 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) in gmu_read64() argument
[all …]
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| D | a6xx_gpu.h | 23 struct a6xx_gmu gmu; member
71 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
73 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
75 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
76 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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| D | a6xx_gpu.c | 24 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
596 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
616 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
622 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
989 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1232 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1234 if (a6xx_gpu->gmu.legacy) { in hw_init()
1236 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); in hw_init()
1248 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_hw_init()
1250 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_hw_init()
[all …]
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| D | a6xx_gpu_state.c | 144 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
752 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
772 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
774 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
801 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
839 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
842 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
844 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
845 struct a6xx_hfi_queue *queue = &gmu->queues[i]; in a6xx_snapshot_gmu_hfi_history()
990 a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); in a6xx_gpu_state_get()
[all …]
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| /linux-6.1.9/Documentation/devicetree/bindings/display/msm/ |
| D | gmu.yaml | 6 $id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
23 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
24 - const: qcom,adreno-gmu
51 - const: gmu
92 - qcom,adreno-gmu-618.0
93 - qcom,adreno-gmu-630.2
103 - const: gmu
114 - const: gmu
124 - qcom,adreno-gmu-635.0
134 - const: gmu
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| D | gpu.yaml | 108 qcom,gmu:
258 qcom,gmu = <&gmu>;
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| /linux-6.1.9/arch/arm64/boot/dts/qcom/ |
| D | msm8992.dtsi | 30 gmu-sram@0 {
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| D | sc7180.dtsi | 1956 qcom,gmu = <&gmu>;
2050 gmu: gmu@506a000 { label
2051 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2054 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2057 interrupt-names = "hfi", "gmu";
2062 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sm8150.dtsi | 2145 qcom,gmu = <&gmu>;
2189 gmu: gmu@2c6a000 { label
2190 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2195 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2199 interrupt-names = "hfi", "gmu";
2206 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sm8150-hdk.dts | 357 &gmu {
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| D | sm8150-mtp.dts | 352 &gmu {
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| D | sm8250-hdk.dts | 367 &gmu {
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| D | sdm845-xiaomi-beryllium.dts | 263 &gmu {
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| D | sdm845.dtsi | 4686 qcom,gmu = <&gmu>;
4762 gmu: gmu@506a000 { label
4763 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4768 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4772 interrupt-names = "hfi", "gmu";
4778 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sm8250.dtsi | 2539 qcom,gmu = <&gmu>;
2588 gmu: gmu@3d6a000 { label
2589 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2595 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2599 interrupt-names = "hfi", "gmu";
2606 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sc7280.dtsi | 2531 qcom,gmu = <&gmu>;
2608 gmu: gmu@3d6a000 { label
2609 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2613 reg-names = "gmu", "rscc", "gmu_pdc";
2616 interrupt-names = "hfi", "gmu";
2624 clock-names = "gmu",
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| D | sdm845-mtp.dts | 502 &gmu {
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| D | sdm845-oneplus-common.dtsi | 366 &gmu {
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| D | sdm850-lenovo-yoga-c630.dts | 340 &gmu {
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| D | sdm845-shift-axolotl.dts | 459 &gmu {
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| D | sdm845-xiaomi-polaris.dts | 421 &gmu {
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| D | sm8250-mtp.dts | 471 &gmu {
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| /linux-6.1.9/Documentation/devicetree/bindings/sram/ |
| D | qcom,ocmem.yaml | 95 gmu-sram@0 {
|