Lines Matching refs:gmu
17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
24 gmu->hung = true; in a6xx_gmu_fault()
35 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
38 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
39 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
42 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
44 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
48 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
51 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
52 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); in a6xx_gmu_irq()
59 struct a6xx_gmu *gmu = data; in a6xx_hfi_irq() local
62 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); in a6xx_hfi_irq()
63 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); in a6xx_hfi_irq()
66 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); in a6xx_hfi_irq()
68 a6xx_gmu_fault(gmu); in a6xx_hfi_irq()
74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) in a6xx_gmu_sptprac_is_on() argument
79 if (!gmu->initialized) in a6xx_gmu_sptprac_is_on()
82 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); in a6xx_gmu_sptprac_is_on()
90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) in a6xx_gmu_gx_is_on() argument
95 if (!gmu->initialized) in a6xx_gmu_gx_is_on()
98 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); in a6xx_gmu_gx_is_on()
110 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_set_freq() local
117 if (gpu_freq == gmu->freq) in a6xx_gmu_set_freq()
120 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) in a6xx_gmu_set_freq()
121 if (gpu_freq == gmu->gpu_freqs[perf_index]) in a6xx_gmu_set_freq()
124 gmu->current_perf_index = perf_index; in a6xx_gmu_set_freq()
125 gmu->freq = gmu->gpu_freqs[perf_index]; in a6xx_gmu_set_freq()
127 trace_msm_gmu_freq_change(gmu->freq, perf_index); in a6xx_gmu_set_freq()
138 if (!gmu->legacy) { in a6xx_gmu_set_freq()
139 a6xx_hfi_set_freq(gmu, perf_index); in a6xx_gmu_set_freq()
144 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); in a6xx_gmu_set_freq()
146 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, in a6xx_gmu_set_freq()
153 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); in a6xx_gmu_set_freq()
156 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); in a6xx_gmu_set_freq()
157 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); in a6xx_gmu_set_freq()
159 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); in a6xx_gmu_set_freq()
161 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); in a6xx_gmu_set_freq()
170 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_get_freq() local
172 return gmu->freq; in a6xx_gmu_get_freq()
175 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) in a6xx_gmu_check_idle_level() argument
178 int local = gmu->idle_level; in a6xx_gmu_check_idle_level()
181 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) in a6xx_gmu_check_idle_level()
184 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); in a6xx_gmu_check_idle_level()
187 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || in a6xx_gmu_check_idle_level()
188 !a6xx_gmu_gx_is_on(gmu)) in a6xx_gmu_check_idle_level()
196 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) in a6xx_gmu_wait_for_idle() argument
198 return spin_until(a6xx_gmu_check_idle_level(gmu)); in a6xx_gmu_wait_for_idle()
201 static int a6xx_gmu_start(struct a6xx_gmu *gmu) in a6xx_gmu_start() argument
207 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); in a6xx_gmu_start()
216 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); in a6xx_gmu_start()
221 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); in a6xx_gmu_start()
223 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); in a6xx_gmu_start()
225 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, in a6xx_gmu_start()
229 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); in a6xx_gmu_start()
234 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) in a6xx_gmu_hfi_start() argument
239 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); in a6xx_gmu_hfi_start()
241 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, in a6xx_gmu_hfi_start()
244 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); in a6xx_gmu_hfi_start()
294 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) in a6xx_gmu_set_oob() argument
300 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); in a6xx_gmu_set_oob()
305 if (gmu->legacy) { in a6xx_gmu_set_oob()
312 DRM_DEV_ERROR(gmu->dev, in a6xx_gmu_set_oob()
320 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); in a6xx_gmu_set_oob()
323 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_gmu_set_oob()
327 DRM_DEV_ERROR(gmu->dev, in a6xx_gmu_set_oob()
330 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); in a6xx_gmu_set_oob()
333 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); in a6xx_gmu_set_oob()
339 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) in a6xx_gmu_clear_oob() argument
343 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); in a6xx_gmu_clear_oob()
348 if (gmu->legacy) in a6xx_gmu_clear_oob()
353 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); in a6xx_gmu_clear_oob()
357 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) in a6xx_sptprac_enable() argument
362 if (!gmu->legacy) in a6xx_sptprac_enable()
365 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); in a6xx_sptprac_enable()
367 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, in a6xx_sptprac_enable()
371 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", in a6xx_sptprac_enable()
372 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); in a6xx_sptprac_enable()
379 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) in a6xx_sptprac_disable() argument
384 if (!gmu->legacy) in a6xx_sptprac_disable()
388 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); in a6xx_sptprac_disable()
390 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); in a6xx_sptprac_disable()
392 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, in a6xx_sptprac_disable()
396 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", in a6xx_sptprac_disable()
397 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); in a6xx_sptprac_disable()
401 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) in a6xx_gmu_gfx_rail_on() argument
406 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); in a6xx_gmu_gfx_rail_on()
409 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; in a6xx_gmu_gfx_rail_on()
411 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); in a6xx_gmu_gfx_rail_on()
412 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); in a6xx_gmu_gfx_rail_on()
415 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_gfx_rail_on()
419 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) in a6xx_gmu_notify_slumber() argument
424 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); in a6xx_gmu_notify_slumber()
427 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) in a6xx_gmu_notify_slumber()
428 a6xx_sptprac_disable(gmu); in a6xx_gmu_notify_slumber()
430 if (!gmu->legacy) { in a6xx_gmu_notify_slumber()
431 ret = a6xx_hfi_send_prep_slumber(gmu); in a6xx_gmu_notify_slumber()
436 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); in a6xx_gmu_notify_slumber()
438 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_notify_slumber()
439 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_notify_slumber()
443 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) in a6xx_gmu_notify_slumber()
445 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); in a6xx_gmu_notify_slumber()
452 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_gmu_notify_slumber()
456 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) in a6xx_rpmh_start() argument
461 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); in a6xx_rpmh_start()
465 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, in a6xx_rpmh_start()
468 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); in a6xx_rpmh_start()
472 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, in a6xx_rpmh_start()
476 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); in a6xx_rpmh_start()
480 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_start()
483 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); in a6xx_rpmh_start()
484 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); in a6xx_rpmh_start()
487 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); in a6xx_rpmh_start()
491 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) in a6xx_rpmh_stop() argument
496 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); in a6xx_rpmh_stop()
498 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, in a6xx_rpmh_stop()
501 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); in a6xx_rpmh_stop()
503 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_stop()
514 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) in a6xx_gmu_rpmh_init() argument
516 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_rpmh_init()
518 struct platform_device *pdev = to_platform_device(gmu->dev); in a6xx_gmu_rpmh_init()
543 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); in a6xx_gmu_rpmh_init()
546 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); in a6xx_gmu_rpmh_init()
547 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); in a6xx_gmu_rpmh_init()
548 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); in a6xx_gmu_rpmh_init()
549 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); in a6xx_gmu_rpmh_init()
550 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); in a6xx_gmu_rpmh_init()
551 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); in a6xx_gmu_rpmh_init()
552 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); in a6xx_gmu_rpmh_init()
553 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); in a6xx_gmu_rpmh_init()
554 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); in a6xx_gmu_rpmh_init()
555 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); in a6xx_gmu_rpmh_init()
556 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); in a6xx_gmu_rpmh_init()
560 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); in a6xx_gmu_rpmh_init()
561 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); in a6xx_gmu_rpmh_init()
562 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); in a6xx_gmu_rpmh_init()
563 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); in a6xx_gmu_rpmh_init()
564 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); in a6xx_gmu_rpmh_init()
566 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); in a6xx_gmu_rpmh_init()
567 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); in a6xx_gmu_rpmh_init()
568 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); in a6xx_gmu_rpmh_init()
569 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); in a6xx_gmu_rpmh_init()
570 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); in a6xx_gmu_rpmh_init()
640 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) in a6xx_gmu_power_config() argument
643 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); in a6xx_gmu_power_config()
644 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); in a6xx_gmu_power_config()
645 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); in a6xx_gmu_power_config()
647 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); in a6xx_gmu_power_config()
649 switch (gmu->idle_level) { in a6xx_gmu_power_config()
651 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, in a6xx_gmu_power_config()
653 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
658 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, in a6xx_gmu_power_config()
660 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
666 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, in a6xx_gmu_power_config()
698 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) in a6xx_gmu_fw_load() argument
700 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fw_load()
712 if (gmu->legacy) { in a6xx_gmu_fw_load()
715 DRM_DEV_ERROR(gmu->dev, in a6xx_gmu_fw_load()
720 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, in a6xx_gmu_fw_load()
734 gmu_write_bulk(gmu, in a6xx_gmu_fw_load()
739 gmu_write_bulk(gmu, in a6xx_gmu_fw_load()
742 } else if (!fw_block_mem(&gmu->icache, blk) && in a6xx_gmu_fw_load()
743 !fw_block_mem(&gmu->dcache, blk) && in a6xx_gmu_fw_load()
744 !fw_block_mem(&gmu->dummy, blk)) { in a6xx_gmu_fw_load()
745 DRM_DEV_ERROR(gmu->dev, in a6xx_gmu_fw_load()
754 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) in a6xx_gmu_fw_start() argument
757 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fw_start()
763 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); in a6xx_gmu_fw_start()
764 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); in a6xx_gmu_fw_start()
768 ret = a6xx_rpmh_start(gmu); in a6xx_gmu_fw_start()
777 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); in a6xx_gmu_fw_start()
781 a6xx_gmu_rpmh_init(gmu); in a6xx_gmu_fw_start()
784 ret = a6xx_rpmh_start(gmu); in a6xx_gmu_fw_start()
789 ret = a6xx_gmu_fw_load(gmu); in a6xx_gmu_fw_start()
794 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); in a6xx_gmu_fw_start()
795 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); in a6xx_gmu_fw_start()
798 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); in a6xx_gmu_fw_start()
799 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); in a6xx_gmu_fw_start()
801 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, in a6xx_gmu_fw_start()
809 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); in a6xx_gmu_fw_start()
811 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, in a6xx_gmu_fw_start()
812 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); in a6xx_gmu_fw_start()
815 a6xx_gmu_power_config(gmu); in a6xx_gmu_fw_start()
817 ret = a6xx_gmu_start(gmu); in a6xx_gmu_fw_start()
821 if (gmu->legacy) { in a6xx_gmu_fw_start()
822 ret = a6xx_gmu_gfx_rail_on(gmu); in a6xx_gmu_fw_start()
828 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { in a6xx_gmu_fw_start()
829 ret = a6xx_sptprac_enable(gmu); in a6xx_gmu_fw_start()
834 ret = a6xx_gmu_hfi_start(gmu); in a6xx_gmu_fw_start()
852 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) in a6xx_gmu_irq_disable() argument
854 disable_irq(gmu->gmu_irq); in a6xx_gmu_irq_disable()
855 disable_irq(gmu->hfi_irq); in a6xx_gmu_irq_disable()
857 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); in a6xx_gmu_irq_disable()
858 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); in a6xx_gmu_irq_disable()
861 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) in a6xx_gmu_rpmh_off() argument
866 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, in a6xx_gmu_rpmh_off()
868 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, in a6xx_gmu_rpmh_off()
870 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, in a6xx_gmu_rpmh_off()
872 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, in a6xx_gmu_rpmh_off()
914 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) in a6xx_gmu_force_off() argument
916 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_force_off()
921 a6xx_hfi_stop(gmu); in a6xx_gmu_force_off()
924 a6xx_gmu_irq_disable(gmu); in a6xx_gmu_force_off()
927 a6xx_sptprac_disable(gmu); in a6xx_gmu_force_off()
930 a6xx_gmu_rpmh_off(gmu); in a6xx_gmu_force_off()
933 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); in a6xx_gmu_force_off()
942 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) in a6xx_gmu_set_initial_freq() argument
945 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; in a6xx_gmu_set_initial_freq()
951 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ in a6xx_gmu_set_initial_freq()
956 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) in a6xx_gmu_set_initial_bw() argument
959 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; in a6xx_gmu_set_initial_bw()
973 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_resume() local
976 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) in a6xx_gmu_resume()
979 gmu->hung = false; in a6xx_gmu_resume()
982 pm_runtime_get_sync(gmu->dev); in a6xx_gmu_resume()
989 if (!IS_ERR_OR_NULL(gmu->gxpd)) in a6xx_gmu_resume()
990 pm_runtime_get_sync(gmu->gxpd); in a6xx_gmu_resume()
993 clk_set_rate(gmu->core_clk, 200000000); in a6xx_gmu_resume()
994 clk_set_rate(gmu->hub_clk, 150000000); in a6xx_gmu_resume()
995 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); in a6xx_gmu_resume()
997 pm_runtime_put(gmu->gxpd); in a6xx_gmu_resume()
998 pm_runtime_put(gmu->dev); in a6xx_gmu_resume()
1003 a6xx_gmu_set_initial_bw(gpu, gmu); in a6xx_gmu_resume()
1006 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); in a6xx_gmu_resume()
1007 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); in a6xx_gmu_resume()
1008 enable_irq(gmu->gmu_irq); in a6xx_gmu_resume()
1011 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? in a6xx_gmu_resume()
1018 if (!gmu->legacy) in a6xx_gmu_resume()
1021 ret = a6xx_gmu_fw_start(gmu, status); in a6xx_gmu_resume()
1025 ret = a6xx_hfi_start(gmu, status); in a6xx_gmu_resume()
1033 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); in a6xx_gmu_resume()
1034 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); in a6xx_gmu_resume()
1035 enable_irq(gmu->hfi_irq); in a6xx_gmu_resume()
1038 a6xx_gmu_set_initial_freq(gpu, gmu); in a6xx_gmu_resume()
1043 disable_irq(gmu->gmu_irq); in a6xx_gmu_resume()
1044 a6xx_rpmh_stop(gmu); in a6xx_gmu_resume()
1045 pm_runtime_put(gmu->gxpd); in a6xx_gmu_resume()
1046 pm_runtime_put(gmu->dev); in a6xx_gmu_resume()
1052 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) in a6xx_gmu_isidle() argument
1056 if (!gmu->initialized) in a6xx_gmu_isidle()
1059 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); in a6xx_gmu_isidle()
1068 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) in a6xx_gmu_shutdown() argument
1070 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_shutdown()
1078 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); in a6xx_gmu_shutdown()
1081 int ret = a6xx_gmu_wait_for_idle(gmu); in a6xx_gmu_shutdown()
1085 a6xx_gmu_force_off(gmu); in a6xx_gmu_shutdown()
1092 ret = a6xx_gmu_notify_slumber(gmu); in a6xx_gmu_shutdown()
1094 a6xx_gmu_force_off(gmu); in a6xx_gmu_shutdown()
1098 ret = gmu_poll_timeout(gmu, in a6xx_gmu_shutdown()
1109 DRM_DEV_ERROR(gmu->dev, in a6xx_gmu_shutdown()
1111 gmu_read(gmu, in a6xx_gmu_shutdown()
1113 gmu_read(gmu, in a6xx_gmu_shutdown()
1118 a6xx_hfi_stop(gmu); in a6xx_gmu_shutdown()
1121 a6xx_gmu_irq_disable(gmu); in a6xx_gmu_shutdown()
1124 a6xx_rpmh_stop(gmu); in a6xx_gmu_shutdown()
1130 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_stop() local
1133 if (!pm_runtime_active(gmu->dev)) in a6xx_gmu_stop()
1140 if (gmu->hung) in a6xx_gmu_stop()
1141 a6xx_gmu_force_off(gmu); in a6xx_gmu_stop()
1143 a6xx_gmu_shutdown(gmu); in a6xx_gmu_stop()
1153 if (!IS_ERR_OR_NULL(gmu->gxpd)) in a6xx_gmu_stop()
1154 pm_runtime_put_sync(gmu->gxpd); in a6xx_gmu_stop()
1156 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); in a6xx_gmu_stop()
1158 pm_runtime_put_sync(gmu->dev); in a6xx_gmu_stop()
1163 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) in a6xx_gmu_memory_free() argument
1165 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace); in a6xx_gmu_memory_free()
1166 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace); in a6xx_gmu_memory_free()
1167 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace); in a6xx_gmu_memory_free()
1168 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace); in a6xx_gmu_memory_free()
1169 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace); in a6xx_gmu_memory_free()
1170 msm_gem_kernel_put(gmu->log.obj, gmu->aspace); in a6xx_gmu_memory_free()
1172 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); in a6xx_gmu_memory_free()
1173 msm_gem_address_space_put(gmu->aspace); in a6xx_gmu_memory_free()
1176 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, in a6xx_gmu_memory_alloc() argument
1179 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_memory_alloc()
1202 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, in a6xx_gmu_memory_alloc()
1217 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) in a6xx_gmu_memory_probe() argument
1226 mmu = msm_iommu_new(gmu->dev, domain); in a6xx_gmu_memory_probe()
1227 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); in a6xx_gmu_memory_probe()
1228 if (IS_ERR(gmu->aspace)) { in a6xx_gmu_memory_probe()
1230 return PTR_ERR(gmu->aspace); in a6xx_gmu_memory_probe()
1335 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) in a6xx_gmu_rpmh_votes_init() argument
1337 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_rpmh_votes_init()
1343 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, in a6xx_gmu_rpmh_votes_init()
1344 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); in a6xx_gmu_rpmh_votes_init()
1347 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, in a6xx_gmu_rpmh_votes_init()
1348 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); in a6xx_gmu_rpmh_votes_init()
1385 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) in a6xx_gmu_pwrlevels_probe() argument
1387 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_pwrlevels_probe()
1397 ret = devm_pm_opp_of_add_table(gmu->dev); in a6xx_gmu_pwrlevels_probe()
1399 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); in a6xx_gmu_pwrlevels_probe()
1403 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, in a6xx_gmu_pwrlevels_probe()
1404 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); in a6xx_gmu_pwrlevels_probe()
1410 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, in a6xx_gmu_pwrlevels_probe()
1411 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); in a6xx_gmu_pwrlevels_probe()
1413 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; in a6xx_gmu_pwrlevels_probe()
1416 return a6xx_gmu_rpmh_votes_init(gmu); in a6xx_gmu_pwrlevels_probe()
1419 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) in a6xx_gmu_clocks_probe() argument
1421 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); in a6xx_gmu_clocks_probe()
1426 gmu->nr_clocks = ret; in a6xx_gmu_clocks_probe()
1428 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, in a6xx_gmu_clocks_probe()
1429 gmu->nr_clocks, "gmu"); in a6xx_gmu_clocks_probe()
1431 gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks, in a6xx_gmu_clocks_probe()
1432 gmu->nr_clocks, "hub"); in a6xx_gmu_clocks_probe()
1458 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, in a6xx_gmu_get_irq() argument
1465 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); in a6xx_gmu_get_irq()
1479 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_remove() local
1480 struct platform_device *pdev = to_platform_device(gmu->dev); in a6xx_gmu_remove()
1482 if (!gmu->initialized) in a6xx_gmu_remove()
1485 pm_runtime_force_suspend(gmu->dev); in a6xx_gmu_remove()
1487 if (!IS_ERR_OR_NULL(gmu->gxpd)) { in a6xx_gmu_remove()
1488 pm_runtime_disable(gmu->gxpd); in a6xx_gmu_remove()
1489 dev_pm_domain_detach(gmu->gxpd, false); in a6xx_gmu_remove()
1492 iounmap(gmu->mmio); in a6xx_gmu_remove()
1494 iounmap(gmu->rscc); in a6xx_gmu_remove()
1495 gmu->mmio = NULL; in a6xx_gmu_remove()
1496 gmu->rscc = NULL; in a6xx_gmu_remove()
1498 a6xx_gmu_memory_free(gmu); in a6xx_gmu_remove()
1500 free_irq(gmu->gmu_irq, gmu); in a6xx_gmu_remove()
1501 free_irq(gmu->hfi_irq, gmu); in a6xx_gmu_remove()
1504 put_device(gmu->dev); in a6xx_gmu_remove()
1506 gmu->initialized = false; in a6xx_gmu_remove()
1512 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_init() local
1519 mutex_init(&gmu->lock); in a6xx_gmu_init()
1521 gmu->dev = &pdev->dev; in a6xx_gmu_init()
1523 of_dma_configure(gmu->dev, node, true); in a6xx_gmu_init()
1526 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; in a6xx_gmu_init()
1528 pm_runtime_enable(gmu->dev); in a6xx_gmu_init()
1531 ret = a6xx_gmu_clocks_probe(gmu); in a6xx_gmu_init()
1535 ret = a6xx_gmu_memory_probe(gmu); in a6xx_gmu_init()
1546 gmu->dummy.size = SZ_4K; in a6xx_gmu_init()
1548 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, in a6xx_gmu_init()
1553 gmu->dummy.size = SZ_8K; in a6xx_gmu_init()
1557 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, in a6xx_gmu_init()
1564 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, in a6xx_gmu_init()
1575 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, in a6xx_gmu_init()
1580 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, in a6xx_gmu_init()
1586 gmu->legacy = true; in a6xx_gmu_init()
1589 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug"); in a6xx_gmu_init()
1595 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); in a6xx_gmu_init()
1600 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0, "log"); in a6xx_gmu_init()
1605 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); in a6xx_gmu_init()
1606 if (IS_ERR(gmu->mmio)) { in a6xx_gmu_init()
1607 ret = PTR_ERR(gmu->mmio); in a6xx_gmu_init()
1612 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); in a6xx_gmu_init()
1613 if (IS_ERR(gmu->rscc)) in a6xx_gmu_init()
1616 gmu->rscc = gmu->mmio + 0x23000; in a6xx_gmu_init()
1620 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); in a6xx_gmu_init()
1621 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); in a6xx_gmu_init()
1623 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) in a6xx_gmu_init()
1630 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); in a6xx_gmu_init()
1633 a6xx_gmu_pwrlevels_probe(gmu); in a6xx_gmu_init()
1636 a6xx_hfi_init(gmu); in a6xx_gmu_init()
1638 gmu->initialized = true; in a6xx_gmu_init()
1643 iounmap(gmu->mmio); in a6xx_gmu_init()
1645 iounmap(gmu->rscc); in a6xx_gmu_init()
1646 free_irq(gmu->gmu_irq, gmu); in a6xx_gmu_init()
1647 free_irq(gmu->hfi_irq, gmu); in a6xx_gmu_init()
1652 a6xx_gmu_memory_free(gmu); in a6xx_gmu_init()
1655 put_device(gmu->dev); in a6xx_gmu_init()