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Searched refs:WREG32_SOC15_IP (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dsdma_v6_0.c236 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
239 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
409 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_stop()
412 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); in sdma_v6_0_gfx_stop()
461 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()
488 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v6_0_gfx_resume()
500 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_resume()
503 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v6_0_gfx_resume()
504 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); in sdma_v6_0_gfx_resume()
505 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); in sdma_v6_0_gfx_resume()
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Dsdma_v5_2.c425 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_stop()
428 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_2_gfx_stop()
483 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_2_ctx_switch_enable()
485 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
487 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
552 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v5_2_gfx_resume()
563 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_resume()
566 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume()
567 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_2_gfx_resume()
568 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume()
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Dsdma_v5_0.c417 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
420 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
595 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop()
598 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_stop()
659 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_0_ctx_switch_enable()
661 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_0_ctx_switch_enable()
663 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_0_ctx_switch_enable()
735 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_resume()
738 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_0_gfx_resume()
739 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_0_gfx_resume()
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Damdgpu_gmc.c614 WREG32_SOC15_IP(GC, reg, tmp) : in amdgpu_gmc_set_vm_fault_masks()
615 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
Dgmc_v9_0.c495 WREG32_SOC15_IP(GC, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
497 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
515 WREG32_SOC15_IP(GC, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
517 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
Dsoc15_common.h75 #define WREG32_SOC15_IP(ip, reg, value) \ macro
Damdgpu_amdkfd_gfx_v10.c225 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in kgd_hqd_load()
Damdgpu_amdkfd_gfx_v10_3.c212 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in hqd_load_v10_3()
Dgfx_v11_0.c5742 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5750 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5799 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
5807 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6013 WREG32_SOC15_IP(GC, target, tmp);
6023 WREG32_SOC15_IP(GC, target, tmp);
Dsoc15.c496 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); in soc15_program_register_sequence()
Dgfx_v10_0.c8976 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
8982 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9029 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9035 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9254 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
9264 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
Dgfx_v9_0.c5569 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5575 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()