Home
last modified time | relevance | path

Searched refs:VC4_SET_FIELD (Results 1 – 13 of 13) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/vc4/
Dvc4_hdmi_phy.c399 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT)); in vc5_hdmi_phy_init()
404 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT)); in vc5_hdmi_phy_init()
407 VC4_SET_FIELD(phy_get_rm_offset(vco_freq), in vc5_hdmi_phy_init()
412 VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO)); in vc5_hdmi_phy_init()
415 VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) | in vc5_hdmi_phy_init()
416 VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD)); in vc5_hdmi_phy_init()
422 VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL)); in vc5_hdmi_phy_init()
427 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) | in vc5_hdmi_phy_init()
428 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) | in vc5_hdmi_phy_init()
429 VC4_SET_FIELD(0x8a, VC4_HDMI_TX_PHY_PLL_CTL_1_CPP)); in vc5_hdmi_phy_init()
[all …]
Dvc4_plane.c434 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | in vc4_write_tpz()
435 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); in vc4_write_tpz()
437 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); in vc4_write_tpz()
446 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | in vc4_write_ppf()
447 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); in vc4_write_ppf()
672 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED, in vc4_hvs4_get_alpha_blend_mode()
677 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED, in vc4_hvs4_get_alpha_blend_mode()
681 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE, in vc4_hvs4_get_alpha_blend_mode()
685 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE, in vc4_hvs4_get_alpha_blend_mode()
693 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED, in vc4_hvs5_get_alpha_blend_mode()
[all …]
Dvc4_dsi.c923 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
924 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_encoder_enable()
938 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | in vc4_dsi_encoder_enable()
939 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | in vc4_dsi_encoder_enable()
940 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); in vc4_dsi_encoder_enable()
942 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
943 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_encoder_enable()
944 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | in vc4_dsi_encoder_enable()
945 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | in vc4_dsi_encoder_enable()
946 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | in vc4_dsi_encoder_enable()
[all …]
Dvc4_kms.c167 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
169 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
171 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
174 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
176 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
178 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
181 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
183 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
185 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
190 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
[all …]
Dvc4_dpi.c154 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); in vc4_dpi_encoder_enable()
164 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
168 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
170 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, in vc4_dpi_encoder_enable()
174 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
178 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
182 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, in vc4_dpi_encoder_enable()
Dvc4_hdmi.c1042 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, in vc4_hdmi_csc_setup()
1058 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, in vc4_hdmi_csc_setup()
1166 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, in vc5_hdmi_csc_setup()
1181 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, in vc5_hdmi_csc_setup()
1186 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, in vc5_hdmi_csc_setup()
1189 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, in vc5_hdmi_csc_setup()
1227 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_hdmi_set_timings()
1229 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_hdmi_set_timings()
1231 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); in vc4_hdmi_set_timings()
1232 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_set_timings()
[all …]
Dvc4_crtc.c269 ret |= VC4_SET_FIELD((level >> 6), in vc4_crtc_get_fifo_full_level_bits()
272 return ret | VC4_SET_FIELD(level & 0x3f, in vc4_crtc_get_fifo_full_level_bits()
347 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
349 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
353 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
355 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
359 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + in vc4_crtc_config_pv()
362 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_crtc_config_pv()
365 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_crtc_config_pv()
367 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
[all …]
Dvc4_hvs.c373 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
375 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
379 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
381 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
849 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); in vc4_hvs_bind()
854 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); in vc4_hvs_bind()
859 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); in vc4_hvs_bind()
864 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); in vc4_hvs_bind()
Dvc4_txp.c305 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | in vc4_txp_connector_atomic_commit()
306 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
324 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
325 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
Dvc4_gem.c447 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
448 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
449 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
450 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
462 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_texture_caches()
463 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); in vc4_flush_texture_caches()
Dvc4_validate.c417 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
419 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()
Dvc4_regs.h14 #define VC4_SET_FIELD(value, field) \ macro