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/linux-6.1.9/arch/ia64/kernel/
Dperfmon_itanium.h12 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
15 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
16 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
17 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
18 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
19 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
20 …REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
21 …REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
[all …]
/linux-6.1.9/arch/sparc/include/uapi/asm/
Dpstate.h18 #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
19 #define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable */
20 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
21 #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
22 #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
23 #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
24 #define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
25 #define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
26 #define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
27 #define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */
[all …]
/linux-6.1.9/arch/arm64/include/asm/
Dkvm_arm.h16 #define HCR_TID5 (UL(1) << 58)
17 #define HCR_DCT (UL(1) << 57)
19 #define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
20 #define HCR_AMVOFFEN (UL(1) << 51)
21 #define HCR_FIEN (UL(1) << 47)
22 #define HCR_FWB (UL(1) << 46)
23 #define HCR_API (UL(1) << 41)
24 #define HCR_APK (UL(1) << 40)
25 #define HCR_TEA (UL(1) << 37)
26 #define HCR_TERR (UL(1) << 36)
[all …]
Dpgtable-hwdef.h50 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
60 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
70 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
181 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
183 #define TTBR_CNP_BIT (UL(1) << 0)
190 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
191 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
194 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
195 #define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
198 #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
[all …]
Desr.h73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
83 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
87 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
89 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
91 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
92 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
93 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
94 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
[all …]
/linux-6.1.9/arch/riscv/include/asm/
Dcsr.h13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF _AC(0x00000000, UL)
23 #define SR_FS_INITIAL _AC(0x00002000, UL)
[all …]
/linux-6.1.9/arch/arm/mach-spear/
Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
34 #define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000)
46 #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
51 #define PERIP_GRP2_BASE UL(0xB3000000)
[all …]
/linux-6.1.9/arch/sparc/include/asm/
Ddcu.h8 #define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
9 #define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
10 #define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
11 #define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
12 #define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
13 #define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
14 #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
15 #define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
16 #define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
17 #define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
[all …]
Dsfafsr.h9 #define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
11 #define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
13 #define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
15 #define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
17 #define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
19 #define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
21 #define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
23 #define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
25 #define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
27 #define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
[all …]
Dpgtable_64.h37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
38 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)
39 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)
40 #define MODULES_VADDR _AC(0x0000000010000000,UL)
41 #define MODULES_LEN _AC(0x00000000e0000000,UL)
42 #define MODULES_END _AC(0x00000000f0000000,UL)
43 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
44 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
45 #define VMALLOC_START _AC(0x0000000100000000,UL)
52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
[all …]
Dlsu.h8 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
9 #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
10 #define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
11 #define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
12 #define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
13 #define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
14 #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
15 #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
16 #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
17 #define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
[all …]
Dmmu_64.h11 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
20 #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
22 #define CTX_PGSZ_8KB _AC(0x0,UL)
23 #define CTX_PGSZ_64KB _AC(0x1,UL)
24 #define CTX_PGSZ_512KB _AC(0x2,UL)
25 #define CTX_PGSZ_4MB _AC(0x3,UL)
26 #define CTX_PGSZ_BITS _AC(0x7,UL)
/linux-6.1.9/arch/x86/kernel/cpu/mtrr/
Dcyrix.c244 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
245 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
/linux-6.1.9/arch/sparc/kernel/
Dtraps_32.c151 { ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
152 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
153 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
154 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL };
/linux-6.1.9/arch/mips/include/asm/mach-generic/
Dspaces.h28 # define PHYS_OFFSET _AC(0, UL)
33 #define CAC_BASE _AC(0x80000000, UL)
35 #define IO_BASE _AC(0xa0000000, UL)
38 #define UNCAC_BASE _AC(0xa0000000, UL)
42 #define MAP_BASE _AC(0xc0000000, UL)
49 #define HIGHMEM_START _AC(0x20000000, UL)
61 #define IO_BASE _AC(0x9000000000000000, UL)
65 #define UNCAC_BASE _AC(0x9000000000000000, UL)
69 #define MAP_BASE _AC(0xc000000000000000, UL)
78 #define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
/linux-6.1.9/arch/x86/include/asm/
Dpgtable_64_types.h64 #define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
98 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
100 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
102 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
192 # define MODULES_END _AC(0xffffffffff000000, UL)
194 # define MODULES_END _AC(0xfffffffffe000000, UL)
198 #define ESPFIX_PGD_ENTRY _AC(-2, UL)
201 #define CPU_ENTRY_AREA_PGD _AC(-4, UL)
204 #define EFI_VA_START ( -4 * (_AC(1, UL) << 30))
205 #define EFI_VA_END (-68 * (_AC(1, UL) << 30))
Ddebugreg.h79 set_debugreg(0UL, 7); in hw_breakpoint_disable()
82 set_debugreg(0UL, 0); in hw_breakpoint_disable()
83 set_debugreg(0UL, 1); in hw_breakpoint_disable()
84 set_debugreg(0UL, 2); in hw_breakpoint_disable()
85 set_debugreg(0UL, 3); in hw_breakpoint_disable()
/linux-6.1.9/arch/mips/include/asm/mach-ip27/
Dspaces.h21 #define HSPEC_BASE _AC(0x9000000000000000, UL)
22 #define IO_BASE _AC(0x9200000000000000, UL)
23 #define MSPEC_BASE _AC(0x9400000000000000, UL)
24 #define UNCAC_BASE _AC(0x9600000000000000, UL)
25 #define CAC_BASE _AC(0xa800000000000000, UL)
31 #define HIGHMEM_START (~0UL)
/linux-6.1.9/arch/arm/include/asm/
Dmemory.h29 #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
39 #define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
48 #define TASK_SIZE_26 (UL(1) << 26)
81 #define FDT_FIXED_BASE UL(0xff800000)
92 #define VECTORS_BASE UL(0xffff0000)
108 #define TASK_SIZE UL(0xffffffff)
111 #define TASK_UNMAPPED_BASE UL(0x00000000)
115 #define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
141 #define ITCM_OFFSET UL(0xfffe0000)
142 #define DTCM_OFFSET UL(0xfffe8000)
[all …]
/linux-6.1.9/tools/memory-model/
Dlock.cat20 * UL Unlock: a spin_unlock() event
28 * LKW and UL are write events; UL has Release ordering.
40 let ALL-LOCKS = LKR | LKW | UL | LF | RU
55 empty ([LKW] ; po-loc ; [LKR]) \ (po-loc ; [UL] ; po-loc) as lock-nest
61 * Put lock operations in their appropriate classes, but leave UL out of W
67 let Release = Release | UL
70 (* Match LKW events to their corresponding UL events *)
71 let critical = ([LKW] ; po-loc ; [UL]) \ (po-loc ; [LKW | UL] ; po-loc)
73 flag ~empty UL \ range(critical) as unmatched-unlock
80 let rfi-lf = ([LKW] ; po-loc ; [LF]) \ ([LKW] ; po-loc ; [UL] ; po-loc)
[all …]
/linux-6.1.9/arch/x86/mm/
Ddump_pagetables.c83 [LOW_KERNEL_NR] = { 0UL, "Low Kernel Mapping" },
84 [VMALLOC_START_NR] = { 0UL, "vmalloc() Area" },
85 [VMEMMAP_START_NR] = { 0UL, "Vmemmap" },
91 [KASAN_SHADOW_START_NR] = { 0UL, "KASAN shadow" },
92 [KASAN_SHADOW_END_NR] = { 0UL, "KASAN shadow end" },
95 [LDT_NR] = { 0UL, "LDT remap" },
134 [VMALLOC_START_NR] = { 0UL, "vmalloc() Area" },
135 [VMALLOC_END_NR] = { 0UL, "vmalloc() End" },
137 [PKMAP_BASE_NR] = { 0UL, "Persistent kmap() Area" },
140 [LDT_NR] = { 0UL, "LDT remap" },
[all …]
/linux-6.1.9/drivers/video/fbdev/core/
Dsysfillrect.c33 first = FB_SHIFT_HIGH(p, ~0UL, dst_idx); in bitfill_aligned()
34 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_aligned()
45 if (first!= ~0UL) { in bitfill_aligned()
79 first = FB_SHIFT_HIGH(p, ~0UL, dst_idx); in bitfill_unaligned()
80 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_unaligned()
134 first = FB_SHIFT_HIGH(p, ~0UL, dst_idx); in bitfill_aligned_rev()
135 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_aligned_rev()
145 if (first!=0UL) { in bitfill_aligned_rev()
190 first = FB_SHIFT_HIGH(p, ~0UL, dst_idx); in bitfill_unaligned_rev()
191 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_unaligned_rev()
[all …]
/linux-6.1.9/arch/arm64/kernel/
Dreloc_test_core.c38 { "R_AARCH64_ABS64", absolute_data64, UL(SYM64_ABS_VAL) },
39 { "R_AARCH64_ABS32", absolute_data32, UL(SYM32_ABS_VAL) },
40 { "R_AARCH64_ABS16", absolute_data16, UL(SYM16_ABS_VAL) },
41 { "R_AARCH64_MOVW_SABS_Gn", signed_movw, UL(SYM64_ABS_VAL) },
42 { "R_AARCH64_MOVW_UABS_Gn", unsigned_movw, UL(SYM64_ABS_VAL) },
/linux-6.1.9/tools/include/linux/
Dbits.h10 #define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
35 (((~UL(0)) - (UL(1) << (l)) + 1) & \
36 (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
/linux-6.1.9/include/linux/
Dbits.h10 #define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
35 (((~UL(0)) - (UL(1) << (l)) + 1) & \
36 (~UL(0) >> (BITS_PER_LONG - 1 - (h))))

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