Lines Matching refs:UL
73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
83 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
87 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
89 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
91 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
92 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
93 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
94 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
99 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
101 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
103 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
105 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
120 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
122 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
124 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
126 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
128 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
130 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
132 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
135 #define ESR_ELx_CV (UL(1) << 24)
137 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
138 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
139 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
140 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
141 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
142 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
143 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
144 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
146 #define DISR_EL1_IDS (UL(1) << 24)
164 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
170 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
172 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
174 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
176 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
178 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
180 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
273 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
283 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
285 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
287 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
289 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
291 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
309 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
312 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
315 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
317 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)