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Searched refs:SDMA0_REGISTER_OFFSET (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/radeon/
Dcik_sdma.c71 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_rptr()
95 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_wptr()
116 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_set_wptr()
260 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
310 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
342 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_enable()
375 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_resume()
483 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()
485 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); in cik_sdma_load_microcode()
486 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()
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Dcik.c165 case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET): in cik_get_allowed_info_register()
3327 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
4812 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
4866 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
4954 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
4956 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5157 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5159 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5512 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5513 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
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Dcikd.h1952 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c49 SDMA0_REGISTER_OFFSET,
888 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
891 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
894 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
909 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
912 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
919 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
922 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
1077 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_soft_reset()
1079 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
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Dsdma_v2_4.c62 SDMA0_REGISTER_OFFSET,
970 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
972 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
1014 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1016 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1019 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1021 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
Dsdma_v3_0.c76 SDMA0_REGISTER_OFFSET,
1348 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1350 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1353 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1355 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
Dvid.h26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
Dcikd.h484 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
Dcik.c1052 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
Dvi.c678 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},