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Searched refs:REG_WRITE (Results 1 – 25 of 108) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn30.c102 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
103 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
104 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn30_backdoor_load()
111 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
112 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
113 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn30_backdoor_load()
136 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
137 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
138 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); in dmub_dcn30_setup_windows()
143 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0); in dmub_dcn30_setup_windows()
[all …]
Ddmub_dcn20.c139 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn20_reset()
140 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn20_reset()
141 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn20_reset()
142 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn20_reset()
143 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn20_reset()
149 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); in dmub_dcn20_reset_release()
169 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn20_backdoor_load()
170 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load()
171 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn20_backdoor_load()
178 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn20_backdoor_load()
[all …]
Ddmub_dcn32.c129 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn32_reset()
130 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn32_reset()
131 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn32_reset()
132 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn32_reset()
133 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn32_reset()
138 REG_WRITE(DMCUB_GPINT_DATAIN1, 0); in dmub_dcn32_reset_release()
140 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); in dmub_dcn32_reset_release()
158 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn32_backdoor_load()
159 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_backdoor_load()
160 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn32_backdoor_load()
[all …]
Ddmub_dcn31.c131 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn31_reset()
132 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn31_reset()
133 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn31_reset()
134 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn31_reset()
135 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); in dmub_dcn31_reset()
136 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); in dmub_dcn31_reset()
137 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn31_reset()
147 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); in dmub_dcn31_reset_release()
165 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn31_backdoor_load()
166 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_backdoor_load()
[all …]
/linux-6.1.9/drivers/net/wireless/ath/
Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
69 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ath_hw_keyreset()
[all …]
Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); in ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); in ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); in ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); in ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); in ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); in ath_hw_cycle_counters_update()
160 REG_WRITE(ah, AR_TFCNT, 0); in ath_hw_cycle_counters_update()
[all …]
/linux-6.1.9/drivers/gpu/drm/gma500/
Doaktrail_hdmi.c290 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in oaktrail_crtc_hdmi_mode_set()
295 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
296 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); in oaktrail_crtc_hdmi_mode_set()
297 REG_WRITE(DPLL_STATUS, 0x1); in oaktrail_crtc_hdmi_mode_set()
312 REG_WRITE(DPLL_CTRL, 0x00000008); in oaktrail_crtc_hdmi_mode_set()
313 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); in oaktrail_crtc_hdmi_mode_set()
315 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
316 REG_WRITE(DPLL_UPDATE, 0x80000000); in oaktrail_crtc_hdmi_mode_set()
317 REG_WRITE(DPLL_CLK_ENABLE, 0x80050102); in oaktrail_crtc_hdmi_mode_set()
[all …]
Dgma_display.c89 REG_WRITE(map->stride, fb->pitches[0]); in gma_pipe_set_base()
113 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
122 REG_WRITE(map->base, offset + start); in gma_pipe_set_base()
125 REG_WRITE(map->base, offset); in gma_pipe_set_base()
127 REG_WRITE(map->surf, start); in gma_pipe_set_base()
162 REG_WRITE(palreg + 4 * i, in gma_crtc_load_lut()
223 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
227 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
231 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
240 REG_WRITE(map->cntr, in gma_crtc_dpms()
[all …]
Dcdv_device.c34 REG_WRITE(vga_reg, VGA_DISP_DISABLE); in cdv_disable_vga()
124 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | in cdv_set_brightness()
296 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); in cdv_restore_display_registers()
297 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); in cdv_restore_display_registers()
300 REG_WRITE(DPIO_CFG, 0); in cdv_restore_display_registers()
301 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_restore_display_registers()
305 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
311 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
317 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); in cdv_restore_display_registers()
318 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); in cdv_restore_display_registers()
[all …]
Dcdv_intel_display.c139 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
140 REG_WRITE(SB_PCKT, in cdv_sb_read()
174 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
175 REG_WRITE(SB_DATA, val); in cdv_sb_write()
176 REG_WRITE(SB_PCKT, in cdv_sb_write()
201 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
203 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
226 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
482 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
[all …]
Dpsb_intel_display.c211 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
216 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
217 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
247 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
251 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
252 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
258 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
264 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
266 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
268 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
[all …]
/linux-6.1.9/drivers/net/wireless/ath/ath9k/
Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); in ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); in ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); in ath9k_wow_create_keep_alive_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
237 REG_WRITE(ah, AR_MAC_PCU_WOW4, in ath9k_hw_wow_wakeup()
[all …]
Dar9003_aic.c111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
155 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), in ar9003_aic_gain_table()
160 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), in ar9003_aic_gain_table()
171 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), in ar9003_aic_cal_start()
176 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0); in ar9003_aic_cal_start()
180 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0, in ar9003_aic_cal_start()
190 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1, in ar9003_aic_cal_start()
197 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0, in ar9003_aic_cal_start()
206 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1, in ar9003_aic_cal_start()
[all …]
Dar5008_phy.c98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
236 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
239 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
312 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
313 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
345 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
346 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
356 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
357 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
[all …]
Dhw.c117 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
337 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
338 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
[all …]
Dar9003_mci.c48 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
58 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
61 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); in ar9003_mci_wait_for_interrupt()
234 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); in ar9003_mci_prep_interface()
235 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, in ar9003_mci_prep_interface()
237 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_prep_interface()
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); in ar9003_mci_prep_interface()
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); in ar9003_mci_prep_interface()
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); in ar9003_mci_prep_interface()
275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF); in ar9003_mci_prep_interface()
[all …]
Dar9002_phy.c101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
233 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
240 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
270 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
273 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9002_hw_spur_mitigate()
411 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); in ar9002_hw_antdiv_comb_conf_set()
430 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ar9002_hw_set_bt_ant_diversity()
432 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); in ar9002_hw_set_bt_ant_diversity()
[all …]
Dar9002_hw.c217 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), in ar9002_hw_configpcipowersave()
223 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ar9002_hw_configpcipowersave()
224 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ar9002_hw_configpcipowersave()
227 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); in ar9002_hw_configpcipowersave()
228 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); in ar9002_hw_configpcipowersave()
229 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); in ar9002_hw_configpcipowersave()
235 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); in ar9002_hw_configpcipowersave()
237 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ar9002_hw_configpcipowersave()
238 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ar9002_hw_configpcipowersave()
239 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); in ar9002_hw_configpcipowersave()
[all …]
Dmac.c32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
54 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
123 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); in ath9k_hw_abort_tx_dma()
166 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_abort_tx_dma()
177 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stop_dma_queue()
187 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stop_dma_queue()
[all …]
Dbtcoex.c333 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode); in ath9k_hw_btcoex_enable_3wire()
334 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ath9k_hw_btcoex_enable_3wire()
337 REG_WRITE(ah, AR_BT_COEX_MODE3, btcoex->bt_coex_mode3); in ath9k_hw_btcoex_enable_3wire()
340 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]); in ath9k_hw_btcoex_enable_3wire()
341 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]); in ath9k_hw_btcoex_enable_3wire()
343 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), in ath9k_hw_btcoex_enable_3wire()
346 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights); in ath9k_hw_btcoex_enable_3wire()
351 REG_WRITE(ah, 0x50040, val); in ath9k_hw_btcoex_enable_3wire()
368 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_enable_mci()
383 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_disable_mci()
[all …]
Dani.c135 REG_WRITE(ah, AR_PHY_ERR_1, 0); in ath9k_ani_restart()
136 REG_WRITE(ah, AR_PHY_ERR_2, 0); in ath9k_ani_restart()
137 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
138 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
451 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_enable_mib_counters()
452 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_enable_mib_counters()
453 REG_WRITE(ah, AR_MIBC, in ath9k_enable_mib_counters()
456 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_enable_mib_counters()
457 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_enable_mib_counters()
469 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath9k_hw_disable_mib_counters()
[all …]
Dar9003_phy.c206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
639 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
645 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
647 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
663 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
673 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
674 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
679 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
[all …]
Dar9003_rtt.c40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
78 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
83 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
87 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
96 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
150 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
154 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubbub.c404 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg); in hubbub3_init_watermarks()
405 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg); in hubbub3_init_watermarks()
406 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg); in hubbub3_init_watermarks()
409 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg); in hubbub3_init_watermarks()
410 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg); in hubbub3_init_watermarks()
411 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg); in hubbub3_init_watermarks()
414 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg); in hubbub3_init_watermarks()
415 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg); in hubbub3_init_watermarks()
416 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg); in hubbub3_init_watermarks()
419 REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg); in hubbub3_init_watermarks()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/
Ddce_abm.c70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); in dce_abm_set_pipe()
115 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); in dmcu_set_backlight_level()
131 REG_WRITE(BIOS_SCRATCH_2, s2); in dmcu_set_backlight_level()
142 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); in dce_abm_init()
143 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); in dce_abm_init()
144 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); in dce_abm_init()
145 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); in dce_abm_init()
146 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); in dce_abm_init()

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