Home
last modified time | relevance | path

Searched refs:REG_FLD_MOD (Results 1 – 20 of 20) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/omapdrm/dss/
Dhdmi5_core.c43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi5_core_ddc_init()
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi5_core_ddc_init()
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi5_core_ddc_init()
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi5_core_ddc_init()
60 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi5_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi5_core_ddc_init()
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi5_core_ddc_init()
69 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi5_core_ddc_init()
74 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, in hdmi5_core_ddc_init()
76 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, in hdmi5_core_ddc_init()
[all …]
Dhdmi4_core.c40 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi4_core_ddc_init()
45 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi4_core_ddc_init()
55 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi4_core_ddc_init()
65 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); in hdmi4_core_ddc_init()
91 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, block / 2, 7, 0); in hdmi4_core_ddc_read()
94 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); in hdmi4_core_ddc_read()
97 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, block % 2 ? 0x80 : 0, 7, 0); in hdmi4_core_ddc_read()
100 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, len, 7, 0); in hdmi4_core_ddc_read()
101 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); in hdmi4_core_ddc_read()
105 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); in hdmi4_core_ddc_read()
[all …]
Dhdmi4_cec.c108 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
116 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
128 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi_cec_clear_tx_fifo()
163 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3); in hdmi_cec_adap_enable()
166 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
203 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3); in hdmi_cec_adap_enable()
238 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
288 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4); in hdmi_cec_adap_transmit()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
Dhdmi_phy.c119 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes()
120 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
139 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure()
156 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure()
163 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure()
Ddss.c57 #define REG_FLD_MOD(dss, idx, val, start, end) \ macro
269 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
273 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ in dss_sdi_enable()
285 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable()
313 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
327 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_disable()
431 REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ in dss_select_dispc_clk_source()
461 REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ in dss_select_dsi_clk_source()
481 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
489 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
[all …]
Dhdmi_wp.c74 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
90 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
104 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); in hdmi_wp_video_start()
115 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); in hdmi_wp_video_stop()
135 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, in hdmi_wp_video_config_format()
266 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); in hdmi_wp_audio_enable()
273 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); in hdmi_wp_audio_core_req_enable()
Ddispc.c53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ macro
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
750 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
875 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
1011 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
1022 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1033 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
1048 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
1133 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
1144 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
[all …]
Dhdmi5.c101 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
265 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi_start_audio_stream()
274 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); in hdmi_stop_audio_stream()
451 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi5_bridge_get_edid()
459 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); in hdmi5_bridge_get_edid()
Ddsi.c53 #define REG_FLD_MOD(dsi, idx, val, start, end) \ macro
765 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ in dsi_if_enable()
848 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
851 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); in dsi_set_lp_clk_divisor()
859 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ in dsi_enable_scp_clk()
866 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ in dsi_disable_scp_clk()
886 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1226 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); in dsi_cio_power()
1601 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ in dsi_cio_init()
1608 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); in dsi_cio_init()
[all …]
Dhdmi.h277 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
/linux-6.1.9/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi5_core.c56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
68 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
75 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
80 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
82 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
87 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
89 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
[all …]
Dhdmi4_core.c41 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi_core_ddc_init()
46 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi_core_ddc_init()
56 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); in hdmi_core_ddc_init()
97 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); in hdmi_core_ddc_edid()
100 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); in hdmi_core_ddc_edid()
103 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); in hdmi_core_ddc_edid()
106 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); in hdmi_core_ddc_edid()
107 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); in hdmi_core_ddc_edid()
111 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); in hdmi_core_ddc_edid()
[all …]
Dhdmi_phy.c128 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes()
129 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes()
148 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure()
165 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure()
172 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure()
Ddss.c58 #define REG_FLD_MOD(idx, val, start, end) \ macro
285 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
289 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ in dss_sdi_enable()
301 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable()
329 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
343 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_disable()
417 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ in dss_select_dispc_clk_source()
445 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ in dss_select_dsi_clk_source()
480 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ in dss_select_lcd_clk_source()
616 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); in dss_set_venc_output()
[all …]
Dhdmi_wp.c75 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
91 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
105 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); in hdmi_wp_video_start()
116 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); in hdmi_wp_video_stop()
136 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, in hdmi_wp_video_config_format()
246 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); in hdmi_wp_audio_enable()
253 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); in hdmi_wp_audio_core_req_enable()
Ddispc.c51 #define REG_FLD_MOD(idx, val, start, end) \ macro
276 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
672 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
762 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
773 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
782 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
795 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
886 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
896 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); in dispc_ovl_configure_burst_type()
[all …]
Dhdmi5.c97 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
318 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in read_edid()
322 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); in read_edid()
332 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); in hdmi_start_audio_stream()
341 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); in hdmi_stop_audio_stream()
Ddsi.c113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ macro
1217 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ in dsi_if_enable()
1306 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
1309 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); in dsi_set_lp_clk_divisor()
1319 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ in dsi_enable_scp_clk()
1328 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ in dsi_disable_scp_clk()
1349 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1756 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); in dsi_cio_power()
1981 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); in dsi_cio_enable_lane_override()
1986 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); in dsi_cio_enable_lane_override()
[all …]
Dhdmi.h258 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
/linux-6.1.9/drivers/gpu/drm/tidss/
Dtidss_dispc.c398 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, in REG_FLD_MOD() function
2106 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k2g_plane_init()
2108 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k2g_plane_init()
2157 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); in dispc_k3_plane_init()
2158 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); in dispc_k3_plane_init()
2161 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k3_plane_init()
2163 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k3_plane_init()
2662 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); in dispc_softreset()