53 #define REG_FLD_MOD(dispc, idx, val, start, end)			\  macro
379 	REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low);  in mgr_fld_write()
750 	REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6);  in dispc_wb_go()
875 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);  in dispc_ovl_write_color_conv_coef()
1011 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);  in dispc_ovl_set_zorder()
1022 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);  in dispc_ovl_enable_zorder_planes()
1033 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);  in dispc_ovl_set_pre_mult_alpha()
1048 	REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);  in dispc_ovl_setup_global_alpha()
1133 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);  in dispc_ovl_set_color_mode()
1144 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);  in dispc_ovl_configure_burst_type()
1146 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);  in dispc_ovl_configure_burst_type()
1261 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size,  in dispc_ovl_set_burst_size()
1360 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);  in dispc_ovl_enable_replication()
1514 	REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14);  in dispc_enable_fifomerge()
1574 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);  in dispc_ovl_set_mflag()
1904 			REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),  in dispc_ovl_set_scaling_uv()
1957 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),  in dispc_ovl_set_scaling_uv()
1961 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);  in dispc_ovl_set_scaling_uv()
1963 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);  in dispc_ovl_set_scaling_uv()
2042 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);  in dispc_ovl_set_rotation_attrs()
2044 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),  in dispc_ovl_set_rotation_attrs()
2054 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),  in dispc_ovl_set_rotation_attrs()
2884 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);  in dispc_wb_setup()
2900 		REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);  in dispc_wb_setup()
2916 	REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);  in dispc_ovl_enable()
2927 	REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29);  in dispc_lcd_enable_signal_polarity()
2935 	REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);  in dispc_lcd_enable_signal()
2943 	REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);  in dispc_pck_free_enable()
2963 	REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1);  in dispc_set_loadmode()
2997 		REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18);  in dispc_mgr_enable_alpha_fixed_zorder()
2999 		REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);  in dispc_mgr_enable_alpha_fixed_zorder()
3264 			REG_FLD_MOD(dispc, DISPC_CONTROL,  in dispc_mgr_set_timings()
3793 	REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3);  in dispc_enable_sidle()
3798 	REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3);	/* SIDLEMODE: no idle */  in dispc_disable_sidle()
3952 		REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3);  in _omap_dispc_initial_config()
3960 		REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9);  in _omap_dispc_initial_config()
3971 		REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0);  in _omap_dispc_initial_config()
4687 	REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4);  in dispc_errata_i734_wa()
4725 	REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4);  in dispc_errata_i734_wa()