Searched refs:REG_BIT (Results 1 – 16 of 16) sorted by relevance
13 #define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)14 #define HDCP_CLEAR_KEYS_TRIGGER REG_BIT(30)15 #define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)17 #define HDCP_FUSE_IN_PROGRESS REG_BIT(7)18 #define HDCP_FUSE_ERROR REG_BIT(6)19 #define HDCP_FUSE_DONE REG_BIT(5)20 #define HDCP_KEY_LOAD_STATUS REG_BIT(1)21 #define HDCP_KEY_LOAD_DONE REG_BIT(0)27 #define HDCP_TRANSA_REP_PRESENT REG_BIT(31)28 #define HDCP_TRANSB_REP_PRESENT REG_BIT(30)[all …]
29 #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)30 #define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)31 #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)35 #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)36 #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)37 #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)39 #define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)42 #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)43 #define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)51 #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)[all …]
131 #define AUD_ENABLE_SDP_SPLIT REG_BIT(31)138 #define AUD_PIN_BUF_ENABLE REG_BIT(31)141 #define AUD_TS_CDCLK_M_EN REG_BIT(31)
43 #define DMC_EVT_CTL_ENABLE REG_BIT(31)44 #define DMC_EVT_CTL_RECURRING REG_BIT(30)
154 #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)160 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
49 #define GEN11_MCR_MULTICAST REG_BIT(31)143 #define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)146 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)148 #define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)212 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)321 #define AUX_INV REG_BIT(0)378 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)381 #define TBIMR_FAST_CLIP REG_BIT(5)384 #define DIS_OVER_FETCH_CACHE REG_BIT(1)385 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)[all …]
48 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)49 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)50 #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)51 #define GEN6_BSD_GO_INDICATOR REG_BIT(4)52 #define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)53 #define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)54 #define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)74 #define ASYNC_FLIP_PERF_DISABLE REG_BIT(14)75 #define MI_FLUSH_ENABLE REG_BIT(12)76 #define TGL_NESTED_BB_EN REG_BIT(12)[all …]
135 #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))155 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)156 #define MI_LRI_MMIO_REMAP_EN REG_BIT(17)177 #define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)187 #define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)188 #define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/251 #define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)252 #define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)302 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */367 #define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)[all …]
77 #define GEN6_PTE_VALID REG_BIT(0)83 #define GEN6_PDE_VALID REG_BIT(0)88 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)89 #define BYT_PTE_WRITEABLE REG_BIT(1)131 #define CHV_PPAT_SNOOP REG_BIT(6)
403 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */ in emit_pte()436 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); in emit_pte()
964 poison &= ~REG_BIT(0); in safe_poison()
188 #define LMEM_INIT REG_BIT(7)646 #define PORT_PLL_ENABLE REG_BIT(31)647 #define PORT_PLL_LOCK REG_BIT(30)648 #define PORT_PLL_REF_SEL REG_BIT(27)649 #define PORT_PLL_POWER_ENABLE REG_BIT(26)650 #define PORT_PLL_POWER_STATE REG_BIT(25)667 #define PORT_PLL_RECALIBRATE REG_BIT(14)668 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)686 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)701 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)[all …]
190 #define DG1_QCLK_REFERENCE REG_BIT(10)218 #define DG1_GEAR_TYPE REG_BIT(16)
20 #define REG_BIT(__n) \ macro
147 #define SLPC_GTPERF_TASK_ENABLED REG_BIT(0)148 #define SLPC_DCC_TASK_ENABLED REG_BIT(11)149 #define SLPC_IN_DCC REG_BIT(12)150 #define SLPC_BALANCER_ENABLED REG_BIT(15)151 #define SLPC_IBC_TASK_ENABLED REG_BIT(16)152 #define SLPC_BALANCER_IA_LMT_ENABLED REG_BIT(17)153 #define SLPC_BALANCER_IA_LMT_ACTIVE REG_BIT(18)
60 #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)