Lines Matching refs:REG_BIT
188 #define LMEM_INIT REG_BIT(7)
646 #define PORT_PLL_ENABLE REG_BIT(31)
647 #define PORT_PLL_LOCK REG_BIT(30)
648 #define PORT_PLL_REF_SEL REG_BIT(27)
649 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
650 #define PORT_PLL_POWER_STATE REG_BIT(25)
667 #define PORT_PLL_RECALIBRATE REG_BIT(14)
668 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
686 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
701 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
1021 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
1024 #define CLAIM_ER_CLR REG_BIT(31)
1025 #define CLAIM_ER_OVERFLOW REG_BIT(16)
1125 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
1142 #define MBUS_JOIN REG_BIT(31)
1143 #define MBUS_HASHING_MODE_MASK REG_BIT(30)
1152 #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
1153 #define HDPORT_ENABLED REG_BIT(0)
1238 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
1242 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
1336 #define FBC_CTL_EN REG_BIT(31)
1337 #define FBC_CTL_PERIODIC REG_BIT(30)
1340 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
1341 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
1342 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
1348 #define FBC_CMD_COMPRESS REG_BIT(0)
1350 #define FBC_STAT_COMPRESSING REG_BIT(31)
1351 #define FBC_STAT_COMPRESSED REG_BIT(30)
1352 #define FBC_STAT_MODIFIED REG_BIT(29)
1355 #define FBC_CTL_FENCE_DBL REG_BIT(4)
1361 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
1367 #define FBC_MOD_NUM_VALID REG_BIT(0)
1382 #define DPFC_CTL_EN REG_BIT(31)
1383 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1385 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1388 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
1389 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1390 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
1391 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
1392 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
1401 #define DPFC_RECOMP_STALL_EN REG_BIT(27)
1415 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1416 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
1417 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
1418 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
1419 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
1422 #define FBC_STRIDE_OVERRIDE REG_BIT(15)
1427 #define ILK_FBC_RT_VALID REG_BIT(0)
1428 #define SNB_FBC_FRONT_BUFFER REG_BIT(1)
1432 #define ILK_PABSTRETCH_DIS REG_BIT(21)
1433 #define ILK_SABSTRETCH_DIS REG_BIT(20)
1452 #define SNB_DPFC_FENCE_EN REG_BIT(29)
1465 #define FBC_REND_NUKE REG_BIT(2)
1466 #define FBC_REND_CACHE_CLEAN REG_BIT(1)
1801 #define PROCHOT_MASK REG_BIT(0)
1802 #define THERMAL_LIMIT_MASK REG_BIT(1)
1803 #define RATL_MASK REG_BIT(5)
1804 #define VR_THERMALERT_MASK REG_BIT(6)
1805 #define VR_TDC_MASK REG_BIT(7)
1806 #define POWER_LIMIT_4_MASK REG_BIT(8)
1807 #define POWER_LIMIT_1_MASK REG_BIT(10)
1808 #define POWER_LIMIT_2_MASK REG_BIT(11)
1837 #define TGL_VRH_GATING_DIS REG_BIT(31)
1838 #define DPT_GATING_DIS REG_BIT(22)
1844 #define DPCE_GATING_DIS REG_BIT(17)
1852 #define CURSOR_GATING_DIS REG_BIT(28)
1862 #define PIPEDMC_GATING_DIS REG_BIT(12)
1873 #define PIPE_CRC_ENABLE REG_BIT(31)
1918 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
2016 #define EXITLINE_ENABLE REG_BIT(31)
2026 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
2027 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
2028 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
2031 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
2056 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
2064 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
2065 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
2066 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
2067 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
2068 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
2069 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
2085 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
2086 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
2087 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
2110 #define TRANS_PUSH_EN REG_BIT(31)
2111 #define TRANS_PUSH_SEND REG_BIT(30)
2161 #define TGL_PSR_ERROR REG_BIT(2)
2162 #define TGL_PSR_POST_EXIT REG_BIT(1)
2163 #define TGL_PSR_PRE_ENTRY REG_BIT(0)
2227 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
2228 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
2296 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
2301 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
2302 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
2303 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
2308 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
2309 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
2310 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
2581 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
2582 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
2583 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
2787 #define PP_ON REG_BIT(31)
2795 #define PP_READY REG_BIT(30)
2800 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
2817 #define EDP_FORCE_VDD REG_BIT(3)
2818 #define EDP_BLC_ENABLE REG_BIT(2)
2819 #define PANEL_POWER_RESET REG_BIT(1)
2820 #define PANEL_POWER_ON REG_BIT(0)
3506 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
3507 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
3576 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
3579 #define PIPECONF_ENABLE REG_BIT(31)
3580 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
3581 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
3582 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
3585 #define PIPECONF_PIPE_LOCKED REG_BIT(25)
3586 #define PIPECONF_FORCE_BORDER REG_BIT(25)
3587 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
3611 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
3614 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
3615 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
3616 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
3621 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
3627 #define PIPECONF_DITHER_EN REG_BIT(4)
3713 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
3717 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
3718 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
3719 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
3720 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
3721 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
3733 #define PIPEMISC_DITHER_ENABLE REG_BIT(4)
3750 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
3751 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
3756 #define PIPE_STATUS_UNDERRUN REG_BIT(31)
3757 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
3758 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
3759 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
3762 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
3763 #define PIPEB_HLINE_INT_EN REG_BIT(28)
3764 #define PIPEB_VBLANK_INT_EN REG_BIT(27)
3765 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
3766 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
3767 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
3768 #define PIPE_PSR_INT_EN REG_BIT(22)
3769 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
3770 #define PIPEA_HLINE_INT_EN REG_BIT(20)
3771 #define PIPEA_VBLANK_INT_EN REG_BIT(19)
3772 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
3773 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
3774 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
3775 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
3776 #define PIPEC_HLINE_INT_EN REG_BIT(12)
3777 #define PIPEC_VBLANK_INT_EN REG_BIT(11)
3778 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
3779 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
3780 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
3785 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
3786 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
3787 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
3788 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
3789 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
3790 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
3791 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
3792 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
3793 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
3794 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
3795 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
3796 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
3799 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
3800 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
3801 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
3802 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
3803 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
3804 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
3805 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
3806 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
3807 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
3808 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
3809 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
3810 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
4101 #define WM_LP_ENABLE REG_BIT(31)
4115 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
4151 #define CURSOR_ENABLE REG_BIT(31)
4152 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
4166 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
4167 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4168 #define MCURSOR_ROTATE_180 REG_BIT(15)
4169 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
4180 #define CURSOR_POS_Y_SIGN REG_BIT(31)
4183 #define CURSOR_POS_X_SIGN REG_BIT(15)
4192 #define CUR_FBC_EN REG_BIT(31)
4221 #define DISP_ENABLE REG_BIT(31)
4222 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
4237 #define DISP_STEREO_ENABLE REG_BIT(25)
4238 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4241 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
4242 #define DISP_LINE_DOUBLE REG_BIT(20)
4243 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
4244 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
4245 #define DISP_ROTATE_180 REG_BIT(15)
4246 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
4247 #define DISP_TILED REG_BIT(10)
4248 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
4249 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
4307 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
4350 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
4351 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
4367 #define DVS_ENABLE REG_BIT(31)
4368 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
4369 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
4375 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
4376 #define DVS_SOURCE_KEY REG_BIT(22)
4377 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
4378 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
4384 #define DVS_ROTATE_180 REG_BIT(15)
4385 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
4386 #define DVS_TILED REG_BIT(10)
4387 #define DVS_DEST_KEY REG_BIT(2)
4413 #define DVS_SCALE_ENABLE REG_BIT(31)
4418 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4419 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4460 #define SPRITE_ENABLE REG_BIT(31)
4461 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
4462 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4470 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
4471 #define SPRITE_SOURCE_KEY REG_BIT(22)
4472 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
4473 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
4474 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
4480 #define SPRITE_ROTATE_180 REG_BIT(15)
4481 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
4482 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
4483 #define SPRITE_TILED REG_BIT(10)
4484 #define SPRITE_DEST_KEY REG_BIT(2)
4510 #define SPRITE_SCALE_ENABLE REG_BIT(31)
4515 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4516 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4560 #define SP_ENABLE REG_BIT(31)
4561 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
4574 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
4575 #define SP_SOURCE_KEY REG_BIT(22)
4576 #define SP_YUV_FORMAT_BT709 REG_BIT(18)
4582 #define SP_ROTATE_180 REG_BIT(15)
4583 #define SP_TILED REG_BIT(10)
4584 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */
4608 #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
4707 #define PLANE_CTL_ENABLE REG_BIT(31)
4710 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
4711 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4736 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
4740 #define PLANE_CTL_ORDER_RGBX REG_BIT(20)
4741 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
4742 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
4748 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
4749 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
4750 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
4751 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
4758 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
4759 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
4760 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
4793 #define PLANE_SURF_DECRYPT REG_BIT(2)
4820 #define PLANE_CUS_ENABLE REG_BIT(31)
4821 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
4826 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
4831 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
4839 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
4840 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4841 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
4842 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
4843 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
4850 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
5081 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
5565 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
5572 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
5573 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
5574 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
5575 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
5576 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
5577 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
5578 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
5579 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
5580 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
5581 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
5582 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
5612 #define DG1_MSTR_IRQ REG_BIT(31)
5613 #define DG1_MSTR_TILE(t) REG_BIT(t)
5630 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
5637 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
5683 #define IGNORE_KVMR_PIPE_A REG_BIT(23)
5684 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
5696 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
5697 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
5703 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
5748 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
5749 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
5750 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
5751 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
5752 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
5753 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
5754 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
5755 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
5756 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
5783 #define DBUF_POWER_REQUEST REG_BIT(31)
5784 #define DBUF_POWER_STATE REG_BIT(30)
5799 #define BW_BUDDY_DISABLE REG_BIT(31)
5810 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
5811 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
5814 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
5815 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
5816 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
5817 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
5818 #define ICL_DELAY_PMRSP REG_BIT(22)
5819 #define DISABLE_FLR_SRC REG_BIT(15)
5820 #define MASK_WAKEMEM REG_BIT(13)
5821 #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
5824 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
5825 #define DCPR_MASK_LPMODE REG_BIT(26)
5826 #define DCPR_SEND_RESP_IMM REG_BIT(25)
5827 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
5856 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
5857 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
5858 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
5859 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
5860 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
5957 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
5958 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
5959 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
6278 #define TRANS_ENABLE REG_BIT(31)
6279 #define TRANS_STATE_ENABLE REG_BIT(30)
6500 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
6504 #define TRANS_DP_AUDIO_ONLY REG_BIT(26)
6505 #define TRANS_DP_ENH_FRAMING REG_BIT(18)
6511 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
6512 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
6519 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
6520 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
6521 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
6638 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
6640 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
6856 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
6870 #define TRANS_DDI_HDCP_SELECT REG_BIT(5)
6885 #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
6890 #define DISABLE_DPT_CLK_GATING REG_BIT(1)
6939 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
7152 #define CDCLK_SQUASH_ENABLE REG_BIT(31)
7226 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
7252 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
7432 #define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11)
7535 #define DKL_TX_DP20BITMODE REG_BIT(2)
7612 #define DC_STATE_EN_DC3CO REG_BIT(30)
7613 #define DC_STATE_DC3CO_STATUS REG_BIT(29)
7812 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
7970 #define SGSI_SIDECLK_DIS REG_BIT(17)
7971 #define SGGI_DIS REG_BIT(15)
7972 #define SGR_DIS REG_BIT(13)
8316 #define TCSS_DDI_STATUS_READY REG_BIT(2)
8317 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
8318 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
8339 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
8342 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)