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Searched refs:PLL_CFG0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/drivers/clk/imx/
Dclk-frac-pll.c21 #define PLL_CFG0 0x0 macro
70 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_prepare()
72 writel_relaxed(val, pll->base + PLL_CFG0); in clk_pll_prepare()
82 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_unprepare()
84 writel_relaxed(val, pll->base + PLL_CFG0); in clk_pll_unprepare()
92 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_is_prepared()
104 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_recalc_rate()
177 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_set_rate()
179 writel_relaxed(val, pll->base + PLL_CFG0); in clk_pll_set_rate()
182 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_set_rate()
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Dclk-sscg-pll.c22 #define PLL_CFG0 0x0 macro
102 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_wait_lock()
300 u32 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_is_prepared()
310 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_prepare()
312 writel_relaxed(val, pll->base + PLL_CFG0); in clk_sscg_pll_prepare()
322 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_unprepare()
324 writel_relaxed(val, pll->base + PLL_CFG0); in clk_sscg_pll_unprepare()
343 val = readl(pll->base + PLL_CFG0); in clk_sscg_pll_recalc_rate()
366 val = readl(pll->base + PLL_CFG0); in clk_sscg_pll_set_rate()
369 writel(val, pll->base + PLL_CFG0); in clk_sscg_pll_set_rate()
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