21 #define PLL_CFG0		0x0  macro
70 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_prepare()
72 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_prepare()
82 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_unprepare()
84 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_unprepare()
92 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_is_prepared()
104 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_recalc_rate()
177 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_set_rate()
179 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_set_rate()
182 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_set_rate()
184 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_set_rate()
189 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_set_rate()
191 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_set_rate()