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Searched refs:PHY_CTRL (Results 1 – 16 of 16) sorted by relevance

/linux-6.1.9/drivers/phy/broadcom/
Dphy-bcm-sr-usb.c21 PHY_CTRL, enumerator
29 [PHY_CTRL] = 0x14,
34 [PHY_CTRL] = 0x10,
39 [PHY_CTRL] = 0xc,
134 rd_data = readl(regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
137 writel(rd_data, regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
183 bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
185 bcm_usb_reg32_setbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
/linux-6.1.9/drivers/phy/freescale/
Dphy-fsl-imx8qm-lvds-phy.c21 #define PHY_CTRL 0x0 macro
72 PHY_CTRL, CTRL_INIT_MASK, CTRL_INIT_VAL); in mixel_lvds_phy_init()
117 regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val); in mixel_lvds_phy_power_on()
127 regmap_write(priv->regmap, PHY_CTRL + REG_SET, val); in mixel_lvds_phy_power_on()
154 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
157 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
287 regmap_write(priv->regmap, PHY_CTRL, CTRL_RESET_VAL); in mixel_lvds_phy_reset()
407 regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD); in mixel_lvds_phy_runtime_suspend()
419 regmap_update_bits(priv->regmap, PHY_CTRL, in mixel_lvds_phy_runtime_resume()
Dphy-fsl-imx8-mipi-dphy.c25 #define PHY_CTRL 0x00 macro
395 regmap_write(priv->lvds_regmap, PHY_CTRL, in mixel_dphy_configure_lvds_phy()
545 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, LVDS_EN); in mixel_dphy_power_on_lvds_phy()
602 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, 0); in mixel_dphy_power_off()
/linux-6.1.9/drivers/phy/renesas/
Dphy-rcar-gen3-pcie.c17 #define PHY_CTRL 0x4000 /* R8A77980 only */ macro
49 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0); in r8a77980_phy_pcie_power_on()
57 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN); in r8a77980_phy_pcie_power_off()
/linux-6.1.9/drivers/net/ethernet/intel/e1000/
De1000_ethtool.c1169 e1000_write_phy_reg(hw, PHY_CTRL, 0x8100); in e1000_nonintegrated_phy_loopback()
1181 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_nonintegrated_phy_loopback()
1183 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); in e1000_nonintegrated_phy_loopback()
1189 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_nonintegrated_phy_loopback()
1217 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); in e1000_integrated_phy_loopback()
1219 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); in e1000_integrated_phy_loopback()
1225 e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); in e1000_integrated_phy_loopback()
1295 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_set_phy_loopback()
1297 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); in e1000_set_phy_loopback()
1347 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_loopback_cleanup()
[all …]
De1000_main.c423 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_up_phy()
425 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_up_phy()
460 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_down_phy()
462 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_down_phy()
4705 !e1000_read_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4709 e1000_write_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4720 !e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) { in e1000_smartspeed()
4723 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl); in e1000_smartspeed()
4794 case PHY_CTRL: in e1000_mii_ioctl()
4829 case PHY_CTRL: in e1000_mii_ioctl()
De1000_hw.c1339 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_copper_link_autoneg()
1344 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_copper_link_autoneg()
1667 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); in e1000_phy_force_speed_duplex()
1754 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); in e1000_phy_force_speed_duplex()
1925 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_config_mac_to_phy()
3108 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_phy_reset()
3113 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_phy_reset()
De1000_hw.h2481 #define PHY_CTRL 0x00 /* Control Register */ macro
/linux-6.1.9/drivers/net/ethernet/intel/e1000e/
Dich8lan.c2385 mac_reg = er32(PHY_CTRL); in e1000_oem_bits_config_ich8lan()
3013 phy_ctrl = er32(PHY_CTRL); in e1000_set_d0_lplu_state_ich8lan()
3017 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3038 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3096 phy_ctrl = er32(PHY_CTRL); in e1000_set_d3_lplu_state_ich8lan()
3100 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3137 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
5221 phy_ctrl = er32(PHY_CTRL); in e1000_kmrn_lock_loss_workaround_ich8lan()
5224 ew32(PHY_CTRL, phy_ctrl); in e1000_kmrn_lock_loss_workaround_ich8lan()
5278 reg = er32(PHY_CTRL); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
[all …]
Dphy.c2646 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) in e1000_access_phy_wakeup_reg_bm()
/linux-6.1.9/drivers/mmc/host/
Dsdhci-pci-arasan.c44 #define PHY_CTRL 0x24 macro
/linux-6.1.9/drivers/scsi/hisi_sas/
Dhisi_sas_v1_hw.c126 #define PHY_CTRL (PORT_BASE + 0x14) macro
566 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); in reset_hw_v1_hw()
569 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); in reset_hw_v1_hw()
Dhisi_sas_v2_hw.c181 #define PHY_CTRL (PORT_BASE + 0x14) macro
1266 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); in init_reg_v2_hw()
Dhisi_sas_v3_hw.c199 #define PHY_CTRL (PORT_BASE + 0x14) macro
2831 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
/linux-6.1.9/drivers/mtd/nand/raw/
Dcadence-nand-controller.c262 #define PHY_CTRL 0x2080 macro
1323 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); in cadence_nand_set_timings()
/linux-6.1.9/drivers/media/i2c/ccs/
Dccs-core.c1532 return ccs_write(sensor, PHY_CTRL, val); in ccs_update_phy_ctrl()