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Searched refs:GC_HWIP (Results 1 – 25 of 41) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dsoc15_common.h116 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
123 …uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \
124 …uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \
125 …uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SP…
144 …5_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)
148 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
160 …uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \
161 …uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \
162 …uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_G…
163 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_G…
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Dgmc_v9_0.c605 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
722 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) in gmc_v9_0_use_invalidate_semaphore()
773 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { in gmc_v9_0_flush_gpu_tlb()
841 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
914 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); in gmc_v9_0_flush_gpu_tlb_pasid()
1131 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || in gmc_v9_0_get_vm_pte()
1132 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) && in gmc_v9_0_get_vm_pte()
1137 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) in gmc_v9_0_get_vm_pte()
1481 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_mc_init()
1599 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_sw_init()
[all …]
Dgmc_v10_0.c141 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
241 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
276 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
721 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
842 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_mc_init()
909 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
927 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
1221 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) || in gmc_v10_0_get_clockgating_state()
1222 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) in gmc_v10_0_get_clockgating_state()
Damdgpu_discovery.c172 [GC_HWIP] = GC_HWID,
270 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { in amdgpu_discovery_harvest_config_quirk()
1253 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { in amdgpu_discovery_harvest_ip()
1480 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_common_ip_blocks()
1516 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_common_ip_blocks()
1525 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gmc_ip_blocks()
1561 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gmc_ip_blocks()
1762 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gc_ip_blocks()
1798 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gc_ip_blocks()
1932 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_mes_ip_blocks()
[all …]
Dgfx_v9_0.c893 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_golden_registers()
949 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_init_golden_registers()
950 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) in gfx_v9_0_init_golden_registers()
1099 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_check_fw_write_wait()
1106 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_fw_write_wait()
1206 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && in check_if_enlarge_doorbell_range()
1219 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_if_need_gfxoff()
1352 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gfx_v9_0_load_mec2_fw_bin_support()
1353 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || in gfx_v9_0_load_mec2_fw_bin_support()
1354 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) in gfx_v9_0_load_mec2_fw_bin_support()
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Dmes_v10_1.c300 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; in mes_v10_1_set_hw_resources()
387 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_init_microcode()
644 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
654 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
664 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
673 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
1087 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_kiq_setting()
Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
Damdgpu_display.c710 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
712 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) in convert_tiling_flags_to_modifier()
714 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) in convert_tiling_flags_to_modifier()
723 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
729 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
785 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); in convert_tiling_flags_to_modifier()
822 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && in convert_tiling_flags_to_modifier()
Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
Dgfx_v10_0.c3644 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_spm_golden_registers()
3667 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_golden_registers()
3914 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_fw_write_wait()
3965 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_gfxoff_flag()
3987 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_microcode()
4230 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_rlcg_reg_access_ctrl()
4458 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_gpu_early_init()
4589 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_sw_init()
4849 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || in gfx_v10_0_setup_rb()
4850 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || in gfx_v10_0_setup_rb()
[all …]
Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
Dimu_v11_0.c49 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v11_0_init_microcode()
357 switch (adev->ip_versions[GC_HWIP][0]) { in imu_v11_0_program_rlc_ram()
Dgmc_v11_0.c192 GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_vm_hub()
599 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_set_gfxhub_funcs()
747 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_sw_init()
Dmes_v11_0.c201 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && in mes_v11_0_add_hw_queue()
202 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) in mes_v11_0_add_hw_queue()
376 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; in mes_v11_0_set_hw_resources()
465 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in mes_v11_0_init_microcode()
1343 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) in mes_v11_0_late_init()
Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
Damdgpu_gmc.c521 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_gmc_tmz_set()
583 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in amdgpu_gmc_noretry_set()
Dsoc21.c424 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_need_full_reset()
564 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_common_early_init()
Dsoc15.c482 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
495 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
956 switch (adev->ip_versions[GC_HWIP][0]) { in soc15_common_early_init()
Dsdma_v5_2.c74 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()
79 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()
83 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
Dgfx_v11_0.c267 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_init_golden_registers()
457 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in gfx_v11_0_init_microcode()
556 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in gfx_v11_0_init_toc_microcode()
853 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_gpu_early_init()
1289 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_sw_init()
2503 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2504 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) in gfx_v11_0_wait_for_rlc_autoload_complete()
5038 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_cntl_power_gating()
5067 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_set_powergating_state()
5093 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_set_clockgating_state()
Damdgpu_amdkfd.c712 if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) { in amdgpu_amdkfd_set_compute_idle()
Damdgpu_mes.c1376 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0) && in amdgpu_mes_self_test()
1377 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0) && in amdgpu_mes_self_test()
/linux-6.1.9/drivers/gpu/drm/amd/amdkfd/
Dkfd_device.c288 switch (adev->ip_versions[GC_HWIP][0]) { in kgd2kfd_probe()
417 if (adev->ip_versions[GC_HWIP][0]) in kgd2kfd_probe()
419 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); in kgd2kfd_probe()
/linux-6.1.9/drivers/gpu/drm/amd/pm/
Damdgpu_pm.c1954 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in default_attr_update()
2888 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in amdgpu_hwmon_show_power_label()
3202 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in hwmon_attributes_visible()
3444 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in amdgpu_debugfs_pm_info_pp()

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