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Searched refs:DIVIL_MSR_REG (Results 1 – 7 of 7) sorted by relevance

/linux-6.1.9/arch/mips/loongson2ef/common/cs5536/
Dcs5536_isa.c18 DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
19 DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
20 DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
59 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_enable()
61 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_enable()
74 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_disable()
76 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_disable()
194 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); in pci_isa_write_reg()
199 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); in pci_isa_write_reg()
202 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); in pci_isa_write_reg()
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Dcs5536_mfgpt.c93 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); in timer_interrupt()
121 _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100); in setup_mfgpt0_timer()
124 _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000); in setup_mfgpt0_timer()
127 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); in setup_mfgpt0_timer()
Dcs5536_ohci.c59 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); in pci_ohci_write_reg()
63 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); in pci_ohci_write_reg()
136 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); in pci_ohci_read_reg()
Dcs5536_acc.c50 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); in pci_acc_write_reg()
55 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); in pci_acc_write_reg()
Dcs5536_ide.c62 _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); in pci_ide_write_reg()
64 _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); in pci_ide_write_reg()
/linux-6.1.9/arch/mips/loongson2ef/lemote-2f/
Dreset.c45 _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); in fl2f_reboot()
47 _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); in fl2f_reboot()
57 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); in fl2f_shutdown()
/linux-6.1.9/arch/mips/include/asm/mach-loongson2ef/cs5536/
Dcs5536.h35 #define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) macro