Home
last modified time | relevance | path

Searched refs:DISPLAY_VER (Results 1 – 25 of 61) sorted by relevance

123

/linux-6.1.9/drivers/gpu/drm/i915/display/
Di9xx_plane.c118 else if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_has_fbc()
140 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_plane_has_windowing()
142 else if (DISPLAY_VER(dev_priv) == 4) in i9xx_plane_has_windowing()
209 if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_plane_ctl()
248 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_check_plane_surface()
265 if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { in i9xx_check_plane_surface()
304 } else if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_check_plane_surface()
362 if (DISPLAY_VER(dev_priv) < 5) in i9xx_plane_ctl_crtc()
425 if (DISPLAY_VER(dev_priv) < 4) { in i9xx_plane_update_noarm()
457 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_update_arm()
[all …]
Dintel_fbc.c161 if (DISPLAY_VER(i915) >= 11) in skl_fbc_min_cfb_stride()
185 if (DISPLAY_VER(i915) >= 9) in intel_fbc_cfb_stride()
196 if (DISPLAY_VER(i915) == 7) in intel_fbc_cfb_size()
198 else if (DISPLAY_VER(i915) >= 8) in intel_fbc_cfb_size()
219 (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) in intel_fbc_override_cfb_stride()
235 if (DISPLAY_VER(i915) == 2) in i8xx_fbc_ctl()
298 if (DISPLAY_VER(i915) == 4) { in i8xx_fbc_activate()
407 if (DISPLAY_VER(i915) < 6) in g4x_dpfc_ctl()
606 if (DISPLAY_VER(i915) >= 10) in ivb_fbc_activate()
608 else if (DISPLAY_VER(i915) == 9) in ivb_fbc_activate()
[all …]
Dskl_universal_plane.c236 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) in icl_nv12_y_plane_mask()
245 return DISPLAY_VER(dev_priv) >= 11 && in icl_is_nv12_y_plane()
251 return DISPLAY_VER(dev_priv) >= 11 && in icl_is_hdr_plane()
466 if (DISPLAY_VER(i915) >= 13) { in skl_plane_max_stride()
871 if (DISPLAY_VER(dev_priv) >= 10) in skl_plane_ctl_crtc()
895 if (DISPLAY_VER(dev_priv) < 10) { in skl_plane_ctl()
910 if (DISPLAY_VER(dev_priv) >= 11) in skl_plane_ctl()
920 if (DISPLAY_VER(dev_priv) == 13) in skl_plane_ctl()
931 if (DISPLAY_VER(dev_priv) >= 11) in glk_plane_color_ctl_crtc()
1031 if (DISPLAY_VER(i915) < 12) in skl_plane_aux_dist()
[all …]
Dintel_fifo_underrun.c193 if (DISPLAY_VER(dev_priv) >= 13) in icl_pipe_status_underrun_mask()
208 if (DISPLAY_VER(dev_priv) >= 11) in bdw_set_fifo_underrun_reporting()
294 else if (DISPLAY_VER(dev_priv) == 7) in __intel_set_cpu_fifo_underrun_reporting()
296 else if (DISPLAY_VER(dev_priv) >= 8) in __intel_set_cpu_fifo_underrun_reporting()
417 if (DISPLAY_VER(dev_priv) >= 11) { in intel_cpu_fifo_underrun_irq_handler()
426 if (DISPLAY_VER(dev_priv) >= 11) in intel_cpu_fifo_underrun_irq_handler()
481 else if (DISPLAY_VER(dev_priv) == 7) in intel_check_cpu_fifo_underruns()
Dintel_bw.c90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000); in icl_pcode_read_qgv_point_info()
170 if (DISPLAY_VER(dev_priv) >= 14) in intel_read_qgv_point_info()
188 if (DISPLAY_VER(dev_priv) >= 14) { in icl_get_qgv_points()
213 } else if (DISPLAY_VER(dev_priv) >= 12) { in icl_get_qgv_points()
247 } else if (DISPLAY_VER(dev_priv) == 11) { in icl_get_qgv_points()
447 if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12) in tgl_get_bw_info()
450 if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels) in tgl_get_bw_info()
629 if (DISPLAY_VER(dev_priv) >= 14) in intel_bw_init_hw()
639 else if (DISPLAY_VER(dev_priv) == 12) in intel_bw_init_hw()
641 else if (DISPLAY_VER(dev_priv) == 11) in intel_bw_init_hw()
[all …]
Dskl_watermark.c62 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
68 return DISPLAY_VER(i915) >= 9 && !IS_LP(i915) && in intel_has_sagv()
75 if (DISPLAY_VER(i915) >= 14) { in intel_sagv_block_time()
81 } else if (DISPLAY_VER(i915) >= 12) { in intel_sagv_block_time()
94 } else if (DISPLAY_VER(i915) == 11) { in intel_sagv_block_time()
96 } else if (DISPLAY_VER(i915) == 9 && !IS_LP(i915)) { in intel_sagv_block_time()
112 if (DISPLAY_VER(i915) < 11) in intel_sagv_init()
311 if (DISPLAY_VER(i915) >= 11) in intel_sagv_pre_plane_update()
331 if (DISPLAY_VER(i915) >= 11) in intel_sagv_post_plane_update()
414 if (DISPLAY_VER(i915) >= 12) in intel_crtc_can_enable_sagv()
[all …]
Dintel_crtc.c108 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in intel_crtc_max_vblank_count()
110 else if (DISPLAY_VER(dev_priv) >= 3) in intel_crtc_max_vblank_count()
305 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
319 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
342 else if (DISPLAY_VER(dev_priv) == 4) in intel_crtc_init()
346 else if (DISPLAY_VER(dev_priv) == 3) in intel_crtc_init()
351 if (DISPLAY_VER(dev_priv) >= 8) in intel_crtc_init()
363 if (DISPLAY_VER(dev_priv) >= 11) in intel_crtc_init()
647 if (DISPLAY_VER(dev_priv) >= 11 && in intel_pipe_update_end()
Dintel_ddi.c98 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); in has_buf_trans_select()
103 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); in has_iboost()
188 if (DISPLAY_VER(dev_priv) < 10) { in intel_wait_ddi_buf_active()
439 if (DISPLAY_VER(dev_priv) >= 12) in intel_ddi_transcoder_func_reg_val_get()
511 if (DISPLAY_VER(dev_priv) >= 12) { in intel_ddi_transcoder_func_reg_val_get()
543 if (DISPLAY_VER(dev_priv) >= 11) { in intel_ddi_enable_transcoder_func()
589 if (DISPLAY_VER(dev_priv) >= 11) in intel_ddi_disable_transcoder_func()
603 if (DISPLAY_VER(dev_priv) >= 12) { in intel_ddi_disable_transcoder_func()
772 if (DISPLAY_VER(dev_priv) >= 12) { in intel_ddi_get_encoder_pipes()
913 if (DISPLAY_VER(dev_priv) >= 13) in intel_ddi_enable_pipe_clock()
[all …]
Dintel_display_power.c915 else if (DISPLAY_VER(dev_priv) >= 12) in get_allowed_dc_mask()
919 else if (DISPLAY_VER(dev_priv) >= 9) in get_allowed_dc_mask()
930 DISPLAY_VER(dev_priv) >= 11 ? in get_allowed_dc_mask()
1105 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in icl_mbus_init()
1122 if (DISPLAY_VER(dev_priv) == 12) in icl_mbus_init()
1385 if (DISPLAY_VER(dev_priv) >= 14) in intel_pch_reset_handshake()
1599 if (DISPLAY_VER(dev_priv) == 12) in tgl_bw_buddy_init()
1643 if (DISPLAY_VER(dev_priv) >= 12) in icl_display_core_init()
1653 if (DISPLAY_VER(dev_priv) >= 12) in icl_display_core_init()
1664 if (DISPLAY_VER(dev_priv) >= 12) { in icl_display_core_init()
[all …]
Dintel_psr.c123 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
131 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : in psr_irq_post_exit_bit_get()
139 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : in psr_irq_pre_entry_bit_get()
147 return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : in psr_irq_mask_get()
157 if (DISPLAY_VER(dev_priv) >= 12) in psr_irq_control()
218 if (DISPLAY_VER(dev_priv) >= 12) in intel_psr_irq_handler()
236 if (DISPLAY_VER(dev_priv) >= 9) { in intel_psr_irq_handler()
364 if (DISPLAY_VER(dev_priv) >= 9 && in intel_psr_init_dpcd()
409 if (DISPLAY_VER(dev_priv) >= 8) in intel_psr_enable_sink()
427 if (DISPLAY_VER(dev_priv) >= 11) in intel_psr1_get_tp_time()
[all …]
Dintel_dp_aux.c178 if (DISPLAY_VER(i915) >= 14) in skl_get_aux_send_ctl()
695 if (DISPLAY_VER(dev_priv) >= 14) { in intel_dp_aux_init()
698 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_dp_aux_init()
701 } else if (DISPLAY_VER(dev_priv) >= 9) { in intel_dp_aux_init()
712 if (DISPLAY_VER(dev_priv) >= 9) in intel_dp_aux_init()
721 if (DISPLAY_VER(dev_priv) >= 9) in intel_dp_aux_init()
730 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) in intel_dp_aux_init()
734 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) in intel_dp_aux_init()
Dintel_display.c429 if (DISPLAY_VER(dev_priv) >= 4) { in intel_wait_for_pipe_off()
564 if (DISPLAY_VER(dev_priv) == 13) in intel_enable_transcoder()
623 if (DISPLAY_VER(dev_priv) >= 14) in intel_disable_transcoder()
626 else if (DISPLAY_VER(dev_priv) >= 12) in intel_disable_transcoder()
676 return DISPLAY_VER(dev_priv) < 4 || in intel_plane_uses_fence()
815 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic()
1022 else if (DISPLAY_VER(dev_priv) >= 13) in icl_set_pipe_chicken()
1151 if (DISPLAY_VER(dev_priv) == 9) in needs_nv12_wa()
1162 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) in needs_scalerclk_wa()
1175 DISPLAY_VER(dev_priv) == 11) in needs_cursorclk_wa()
[all …]
Dintel_vrr.c81 if (DISPLAY_VER(i915) >= 13) in intel_vrr_vblank_exit_length()
145 if (DISPLAY_VER(i915) >= 13) { in intel_vrr_compute_config()
182 if (DISPLAY_VER(dev_priv) >= 13) in intel_vrr_enable()
249 if (DISPLAY_VER(dev_priv) >= 13) in intel_vrr_get_config()
Dintel_cdclk.c1454 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1474 if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1491 if (DISPLAY_VER(dev_priv) >= 12) in bxt_get_cdclk()
1493 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_get_cdclk()
1633 if (DISPLAY_VER(dev_priv) >= 12) { in bxt_cdclk_cd2x_pipe()
1638 } else if (DISPLAY_VER(dev_priv) >= 11) { in bxt_cdclk_cd2x_pipe()
1704 if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
1727 } else if (DISPLAY_VER(dev_priv) >= 11) { in bxt_set_cdclk()
1776 if (DISPLAY_VER(dev_priv) >= 11) { in bxt_set_cdclk()
1801 if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
[all …]
Dintel_pipe_crc.c413 if (DISPLAY_VER(dev_priv) == 2) in get_new_crc_ctl_reg()
415 else if (DISPLAY_VER(dev_priv) < 5) in get_new_crc_ctl_reg()
421 else if (DISPLAY_VER(dev_priv) < 9) in get_new_crc_ctl_reg()
543 if (DISPLAY_VER(dev_priv) == 2) in intel_is_valid_crc_source()
545 else if (DISPLAY_VER(dev_priv) < 5) in intel_is_valid_crc_source()
551 else if (DISPLAY_VER(dev_priv) < 9) in intel_is_valid_crc_source()
Dintel_dp_mst.c217 if (DISPLAY_VER(dev_priv) < 12) in intel_dp_mst_transcoder_mask()
269 if (DISPLAY_VER(dev_priv) < 12) in intel_dp_mst_atomic_master_trans_check()
398 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && in intel_mst_post_disable_dp()
414 if (DISPLAY_VER(dev_priv) >= 9) in intel_mst_post_disable_dp()
440 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) in intel_mst_post_disable_dp()
490 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && in intel_mst_pre_enable_dp()
520 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) in intel_mst_pre_enable_dp()
568 if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable) in intel_mst_enable_dp()
571 else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) in intel_mst_enable_dp()
957 if (DISPLAY_VER(i915) < 12 && port == PORT_A) in intel_dp_mst_encoder_init()
[all …]
Dintel_vga.c20 else if (DISPLAY_VER(i915) >= 5) in intel_vga_cntrl_reg()
103 unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; in intel_vga_set_state()
Dintel_fb.c556 else if (DISPLAY_VER(i915) < 11 && in skl_main_to_aux_plane()
565 return DISPLAY_VER(i915) == 2 ? 2048 : 4096; in intel_tile_size()
578 if (DISPLAY_VER(dev_priv) == 2) in intel_tile_width_bytes()
603 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv)) in intel_tile_width_bytes()
708 return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR; in intel_modifier_uses_dpt()
730 if (DISPLAY_VER(dev_priv) >= 9) in intel_linear_alignment()
735 else if (DISPLAY_VER(dev_priv) >= 4) in intel_linear_alignment()
758 if (DISPLAY_VER(dev_priv) >= 12) { in intel_surf_alignment()
1046 if (DISPLAY_VER(i915) >= 12 && in intel_fb_offset_to_xy()
1152 if (DISPLAY_VER(i915) < 4) in intel_plane_can_remap()
[all …]
Dintel_audio.c263 if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
592 if (DISPLAY_VER(i915) < 11) in enable_audio_dsc_wa()
597 if (DISPLAY_VER(i915) == 11) in enable_audio_dsc_wa()
599 else if (DISPLAY_VER(i915) >= 12) in enable_audio_dsc_wa()
941 } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) { in intel_audio_hooks_init()
955 if (DISPLAY_VER(i915) >= 13) in intel_audio_cdclk_change_pre()
973 if (DISPLAY_VER(i915) >= 13) { in intel_audio_cdclk_change_post()
1050 if (DISPLAY_VER(dev_priv) >= 9) { in i915_audio_component_get_power()
1062 if (DISPLAY_VER(dev_priv) >= 10) in i915_audio_component_get_power()
1090 if (DISPLAY_VER(dev_priv) < 9) in i915_audio_component_codec_wake_override()
[all …]
Dintel_cursor.c339 if (DISPLAY_VER(dev_priv) >= 11) in i9xx_cursor_ctl_crtc()
348 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in i9xx_cursor_ctl_crtc()
383 if (DISPLAY_VER(dev_priv) == 13) in i9xx_cursor_ctl()
530 if (DISPLAY_VER(dev_priv) >= 9) in i9xx_cursor_update_arm()
586 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_cursor_get_hw_state()
808 if (DISPLAY_VER(dev_priv) >= 4) in intel_cursor_plane_create()
817 if (DISPLAY_VER(dev_priv) >= 12) in intel_cursor_plane_create()
Dintel_display_power_well.c340 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : in hsw_power_well_enable()
367 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : in hsw_power_well_enable()
408 if (DISPLAY_VER(dev_priv) < 12) { in icl_combo_phy_aux_power_well_enable()
456 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) in icl_tc_port_assert_ref_held()
524 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) in icl_tc_phy_aux_power_well_enable()
529 if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) { in icl_tc_phy_aux_power_well_enable()
594 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && in hsw_power_well_enabled()
689 if (DISPLAY_VER(dev_priv) >= 12) in gen9_dc_mask()
692 else if (DISPLAY_VER(dev_priv) == 11) in gen9_dc_mask()
796 if (DISPLAY_VER(dev_priv) == 12) in assert_can_enable_dc5()
[all …]
Dintel_atomic_plane.c201 return DISPLAY_VER(i915) >= 13 && in use_min_ddb()
425 return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip; in intel_plane_do_async_flip()
442 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
483 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()
490 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()
497 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) { in intel_plane_atomic_calc_changes()
845 if (DISPLAY_VER(i915) >= 9) in intel_crtc_planes_update_arm()
940 if (DISPLAY_VER(to_i915(crtc->dev)) < 6) in add_rps_boost_after_vblank()
/linux-6.1.9/drivers/gpu/drm/i915/
Dintel_device_info.c317 else if (DISPLAY_VER(dev_priv) >= 11) { in intel_device_info_runtime_init()
320 } else if (DISPLAY_VER(dev_priv) >= 9) { in intel_device_info_runtime_init()
328 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) in intel_device_info_runtime_init()
331 else if (DISPLAY_VER(dev_priv) >= 11) in intel_device_info_runtime_init()
334 else if (DISPLAY_VER(dev_priv) == 10) in intel_device_info_runtime_init()
353 } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { in intel_device_info_runtime_init()
386 } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { in intel_device_info_runtime_init()
403 if (DISPLAY_VER(dev_priv) >= 12 && in intel_device_info_runtime_init()
415 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) in intel_device_info_runtime_init()
418 if (DISPLAY_VER(dev_priv) >= 10 && in intel_device_info_runtime_init()
Di915_drv.h180 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
482 #define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver) macro
484 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
849 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
850 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
862 #define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
864 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
869 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
871 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
879 #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
[all …]
Di915_irq.c199 if (DISPLAY_VER(dev_priv) >= 11) in intel_hpd_init_pins()
203 else if (DISPLAY_VER(dev_priv) >= 8) in intel_hpd_init_pins()
205 else if (DISPLAY_VER(dev_priv) >= 7) in intel_hpd_init_pins()
514 if (DISPLAY_VER(dev_priv) < 5) in i915_pipestat_enable_mask()
616 if (DISPLAY_VER(dev_priv) >= 4) in i915_enable_asle_pipestat()
890 bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 || in i915_get_crtc_scanoutpos()
891 IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 || in i915_get_crtc_scanoutpos()
1338 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { in display_pipe_crc_irq_handler()
1400 if (DISPLAY_VER(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
1405 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
[all …]

123