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Searched refs:APBC_PWM1 (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/clk/mmp/
Dclk-of-pxa168.c26 #define APBC_PWM1 0x10 macro
165 …{0, "pwm1_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4,…
186 …{PXA168_CLK_PWM1, "pwm1_clk", "pwm1_mux", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &pwm1_…
Dclk-of-pxa910.c29 #define APBC_PWM1 0x10 macro
144 …{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
Dclk-pxa910.c27 #define APBC_PWM1 0x10 macro
191 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa910_clk_init()
Dclk-pxa168.c27 #define APBC_PWM1 0x10 macro
186 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa168_clk_init()
Dclk-mmp2.c34 #define APBC_PWM1 0x40 macro
231 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in mmp2_clk_init()
Dclk-of-mmp2.c40 #define APBC_PWM1 0x40 macro
259 …{MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lo…