Searched refs:APBC_PWM0 (Results 1 – 6 of 6) sorted by relevance
| /linux-6.1.9/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 25 #define APBC_PWM0 0xc macro
164 …{0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4,…
185 …{PXA168_CLK_PWM0, "pwm0_clk", "pwm0_mux", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &pwm0_…
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| D | clk-of-pxa910.c | 28 #define APBC_PWM0 0xc macro
143 …{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-pxa910.c | 26 #define APBC_PWM0 0xc macro
187 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa910_clk_init()
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| D | clk-pxa168.c | 26 #define APBC_PWM0 0xc macro
182 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 33 #define APBC_PWM0 0x3c macro
227 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in mmp2_clk_init()
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| D | clk-of-mmp2.c | 39 #define APBC_PWM0 0x3c macro
258 …{MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lo…
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