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Searched refs:vlv (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_display_power_map.c197 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
204 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
206 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
208 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
210 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
216 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
278 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
281 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
Dintel_display_power_well.h72 } vlv; member
Dintel_display_types.h863 } vlv; member
1304 struct vlv_wm_state vlv; member
Dintel_display_power_well.c1067 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_set_power_well()
1116 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_power_well_enabled()
/linux-5.19.10/drivers/gpu/drm/i915/
Dintel_pm.c474 dev_priv->wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
505 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
1713 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1714 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1828 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1853 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1872 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1873 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1874 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1883 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
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Di915_drv.h725 struct vlv_wm_values vlv; member