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/linux-5.19.10/Documentation/devicetree/bindings/clock/
Dmediatek,topckgen.yaml4 $id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
14 The Mediatek topckgen controller provides various clocks to the system.
21 - mediatek,mt6797-topckgen
22 - mediatek,mt7622-topckgen
23 - mediatek,mt8135-topckgen
24 - mediatek,mt8173-topckgen
25 - mediatek,mt8516-topckgen
27 - const: mediatek,mt7623-topckgen
28 - const: mediatek,mt2701-topckgen
32 - mediatek,mt2701-topckgen
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/sound/
Dmt2701-afe-pcm.txt69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
Dmtk-afe-pcm.txt26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
Dmt8195-afe-pcm.yaml34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
138 - mediatek,topckgen
157 mediatek,topckgen = <&topckgen>;
161 <&topckgen 163>, //CLK_TOP_APLL1
162 <&topckgen 166>, //CLK_TOP_APLL2
163 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
164 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
165 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
166 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
[all …]
Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
Dmt8192-afe-pcm.yaml34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
64 - mediatek,topckgen
86 mediatek,topckgen = <&topckgen>;
Dmt8183-afe-pcm.txt32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
/linux-5.19.10/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
252 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
253 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
Dmt8192.dtsi264 topckgen: syscon@10000000 { label
265 compatible = "mediatek,mt8192-topckgen", "syscon";
322 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
340 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
382 clocks = <&topckgen CLK_TOP_DISP_SEL>,
396 clocks = <&topckgen CLK_TOP_IPE_SEL>,
409 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
419 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
429 clocks = <&topckgen CLK_TOP_MDP_SEL>,
438 clocks = <&topckgen CLK_TOP_VENC_SEL>,
[all …]
Dmt8195.dtsi288 topckgen: syscon@10000000 { label
289 compatible = "mediatek,mt8195-topckgen", "syscon";
355 clocks = <&topckgen CLK_TOP_CLK26M_D2>;
366 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
367 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
459 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
460 <&topckgen CLK_TOP_SPI>,
473 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
474 <&topckgen CLK_TOP_SPI>,
487 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
[all …]
Dmt7622.dtsi250 clocks = <&topckgen CLK_TOP_HIF_SEL>;
259 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: topckgen@10210000 { label
293 compatible = "mediatek,mt7622-topckgen",
332 clocks = <&topckgen CLK_TOP_RTC>;
396 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
Dmt2712e.dtsi90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
Dmt7986a.dtsi109 topckgen: topckgen@1001b000 { label
110 compatible = "mediatek,mt7986-topckgen", "syscon";
182 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
184 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
185 <&topckgen CLK_TOP_UART_SEL>;
198 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
211 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
245 <&topckgen CLK_TOP_NETSYS_SEL>,
246 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
253 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
[all …]
Dmt8173.dtsi356 topckgen: clock-controller@10000000 { label
357 compatible = "mediatek,mt8173-topckgen";
468 clocks = <&topckgen CLK_TOP_MM_SEL>;
474 clocks = <&topckgen CLK_TOP_MM_SEL>,
475 <&topckgen CLK_TOP_VENC_SEL>;
481 clocks = <&topckgen CLK_TOP_MM_SEL>;
487 clocks = <&topckgen CLK_TOP_MM_SEL>;
494 clocks = <&topckgen CLK_TOP_MM_SEL>,
495 <&topckgen CLK_TOP_VENC_LT_SEL>;
543 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
Dmt8167.dtsi20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
52 clocks = <&topckgen CLK_TOP_SMI_MM>;
60 clocks = <&topckgen CLK_TOP_SMI_MM>,
61 <&topckgen CLK_TOP_RG_VDEC>;
68 clocks = <&topckgen CLK_TOP_SMI_MM>;
75 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
76 <&topckgen CLK_TOP_RG_SLOW_MFG>;
Dmt8183.dtsi434 topckgen: syscon@10000000 { label
435 compatible = "mediatek,mt8183-topckgen", "syscon";
492 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
507 clocks = <&topckgen CLK_TOP_MUX_MFG>;
539 clocks = <&topckgen CLK_TOP_MUX_MM>,
561 clocks = <&topckgen CLK_TOP_MUX_CAM>,
579 clocks = <&topckgen CLK_TOP_MUX_IMG>,
602 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
603 <&topckgen CLK_TOP_MUX_DSP>,
620 clocks = <&topckgen CLK_TOP_MUX_DSP1>;
[all …]
/linux-5.19.10/arch/arm/boot/dts/
Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
Dmt2701.dtsi126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
404 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
Dmt7623.dtsi226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-decoder.yaml143 <&topckgen CLK_TOP_UNIVPLL_D2>,
144 <&topckgen CLK_TOP_CCI400_SEL>,
145 <&topckgen CLK_TOP_VDEC_SEL>,
146 <&topckgen CLK_TOP_VCODECPLL>,
148 <&topckgen CLK_TOP_VENC_LT_SEL>,
149 <&topckgen CLK_TOP_VCODECPLL_370P5>;
158 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
159 <&topckgen CLK_TOP_CCI400_SEL>,
160 <&topckgen CLK_TOP_VDEC_SEL>,
163 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
Dmediatek,vcodec-encoder.yaml155 clocks = <&topckgen CLK_TOP_VENC_SEL>;
157 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
158 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
175 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
177 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
178 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
Dmediatek,vcodec-subdev-decoder.yaml235 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
239 <&topckgen CLK_TOP_MAINPLL_D4>;
241 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
242 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
261 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
265 <&topckgen CLK_TOP_MAINPLL_D4>;
267 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
268 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
/linux-5.19.10/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.yaml162 <&topckgen CLK_TOP_ETHER_125M_SEL>,
163 <&topckgen CLK_TOP_ETHER_50M_SEL>,
164 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
165 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
166 <&topckgen CLK_TOP_ETHER_50M_SEL>,
167 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
168 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
169 <&topckgen CLK_TOP_APLL1_D3>,
170 <&topckgen CLK_TOP_ETHERPLL_50M>;
/linux-5.19.10/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt8186-sys-clock.yaml21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
31 - mediatek,mt8186-topckgen
50 topckgen: syscon@10000000 {
51 compatible = "mediatek,mt8186-topckgen", "syscon";
Dmediatek,mt8195-sys-clock.yaml21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
28 - mediatek,mt8195-topckgen
48 topckgen: syscon@10000000 {
49 compatible = "mediatek,mt8195-topckgen", "syscon";

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