Lines Matching refs:topckgen

434 		topckgen: syscon@10000000 {  label
435 			compatible = "mediatek,mt8183-topckgen", "syscon";
492 					clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
507 					clocks =  <&topckgen CLK_TOP_MUX_MFG>;
539 					clocks = <&topckgen CLK_TOP_MUX_MM>,
561 						clocks = <&topckgen CLK_TOP_MUX_CAM>,
579 						clocks = <&topckgen CLK_TOP_MUX_IMG>,
602 						clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
603 							 <&topckgen CLK_TOP_MUX_DSP>,
620 							clocks = <&topckgen CLK_TOP_MUX_DSP1>;
628 							clocks = <&topckgen CLK_TOP_MUX_DSP2>;
655 			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
677 			clocks = <&topckgen CLK_TOP_CLK13M>;
803 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
804 				 <&topckgen CLK_TOP_MUX_SPI>,
952 			clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
991 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
992 				 <&topckgen CLK_TOP_MUX_SPI>,
1018 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1019 				 <&topckgen CLK_TOP_MUX_SPI>,
1031 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1032 				 <&topckgen CLK_TOP_MUX_SPI>,
1104 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1105 				 <&topckgen CLK_TOP_MUX_SPI>,
1117 			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1118 				 <&topckgen CLK_TOP_MUX_SPI>,
1210 					 <&topckgen CLK_TOP_MUX_AUDIO>,
1211 					 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1212 					 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1213 					 <&topckgen CLK_TOP_MUX_AUD_1>,
1214 					 <&topckgen CLK_TOP_APLL1_CK>,
1215 					 <&topckgen CLK_TOP_MUX_AUD_2>,
1216 					 <&topckgen CLK_TOP_APLL2_CK>,
1217 					 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1218 					 <&topckgen CLK_TOP_APLL1_D8>,
1219 					 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1220 					 <&topckgen CLK_TOP_APLL2_D8>,
1221 					 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1222 					 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1223 					 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1224 					 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1225 					 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1226 					 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1227 					 <&topckgen CLK_TOP_APLL12_DIV0>,
1228 					 <&topckgen CLK_TOP_APLL12_DIV1>,
1229 					 <&topckgen CLK_TOP_APLL12_DIV2>,
1230 					 <&topckgen CLK_TOP_APLL12_DIV3>,
1231 					 <&topckgen CLK_TOP_APLL12_DIV4>,
1232 					 <&topckgen CLK_TOP_APLL12_DIVB>,
1233 					 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1285 			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1297 			clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
1371 			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;