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Searched refs:tf_shift (Results 1 – 23 of 23) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
213 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
215 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
260 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
262 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
264 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
266 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
269 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
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Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
547 const struct dcn_dpp_shift *tf_shift, in dpp1_construct() argument
557 dpp->tf_shift = tf_shift; in dpp1_construct()
Ddcn10_dpp_dscl.c54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
369 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp1_dscl_set_scl_filter()
Ddcn10_resource.c358 static const struct dcn_dpp_shift tf_shift = { variable
590 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
Ddcn10_dpp.h1356 const struct dcn_dpp_shift *tf_shift; member
1518 const struct dcn_dpp_shift *tf_shift,
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp_cm.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
179 reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
181 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
184 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
186 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
188 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
190 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
193 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
195 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
197 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
[all …]
Ddcn30_dpp.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
630 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
632 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field()
634 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
636 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field()
639 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
641 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
643 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
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Ddcn30_dpp.h562 const struct dcn3_dpp_shift *tf_shift; member
581 const struct dcn3_dpp_shift *tf_shift,
Ddcn30_resource.c424 static const struct dcn3_dpp_shift tf_shift = { variable
765 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn30_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
284 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc()
286 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc()
362 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
364 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
366 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
368 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
371 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
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Ddcn20_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
408 const struct dcn2_dpp_shift *tf_shift, in dpp2_construct() argument
418 dpp->tf_shift = tf_shift; in dpp2_construct()
Ddcn20_dpp.h682 const struct dcn2_dpp_shift *tf_shift; member
772 const struct dcn2_dpp_shift *tf_shift,
Ddcn20_resource.c424 static const struct dcn2_dpp_shift tf_shift = { variable
755 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_dpp.h61 const struct dcn201_dpp_shift *tf_shift; member
80 const struct dcn201_dpp_shift *tf_shift,
Ddcn201_dpp.c42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
297 const struct dcn201_dpp_shift *tf_shift, in dpp201_construct() argument
307 dpp->tf_shift = tf_shift; in dpp201_construct()
Ddcn201_resource.c475 static const struct dcn201_dpp_shift tf_shift = { variable
637 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c534 static const struct dcn3_dpp_shift tf_shift = { variable
549 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c495 static const struct dcn3_dpp_shift tf_shift = { variable
510 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c444 static const struct dcn2_dpp_shift tf_shift = { variable
512 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c412 static const struct dcn3_dpp_shift tf_shift = { variable
737 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn315/
Ddcn315_resource.c486 static const struct dcn3_dpp_shift tf_shift = { variable
928 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn316/
Ddcn316_resource.c482 static const struct dcn3_dpp_shift tf_shift = { variable
927 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c485 static const struct dcn3_dpp_shift tf_shift = { variable
933 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()