Searched refs:implemented (Results 1 – 25 of 635) sorted by relevance
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28 These instructions are fully implemented.40 These instructions are fully implemented. They store/load three words58 FLT/FIX are fully implemented.60 RFS/WFS are fully implemented.62 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and73 These are fully implemented.87 These are fully implemented.93 These are fully implemented as well. They use the same algorithm as the103 This is fully implemented.110 These are fully implemented.[all …]
13 Enable this to support USB PHY implemented on USB2 controller25 Enable this to support USB PHY implemented in USB3 controller35 Enable this to support PHY implemented in PCIe controller45 Enable this to support PHY implemented in AHCI controller
7 This document describes the devlink features implemented by the ``bnxt``13 .. list-table:: Generic parameters implemented31 .. list-table:: Driver-specific parameters implemented50 .. list-table:: devlink info versions implemented
7 This document describes the devlink features implemented by the ``mlx5``13 .. list-table:: Generic parameters implemented34 .. list-table:: Driver-specific parameters implemented65 .. list-table:: devlink info versions implemented
7 This document describes the devlink features implemented by the ``mlxsw``13 .. list-table:: Generic parameters implemented23 .. list-table:: Driver-specific parameters implemented45 .. list-table:: devlink info versions implemented
7 This document describes the devlink features implemented by the ``octeontx2 AF, PF and VF``15 .. list-table:: Driver-specific parameters implemented31 .. list-table:: Driver-specific parameters implemented
7 This document describes the devlink features implemented by the ``nfp``13 .. list-table:: Generic parameters implemented27 .. list-table:: devlink info versions implemented
7 This document describes the devlink features implemented by the ``mlx4``13 .. list-table:: Generic parameters implemented27 .. list-table:: Driver-specific parameters implemented
7 This document describes the devlink features implemented by the ``hns3``17 .. list-table:: devlink info versions implemented
7 This document describes the devlink features implemented by the ``am65-cpsw-nuss``16 .. list-table:: Driver-specific parameters implemented
7 This document describes the devlink features implemented by the ``qed`` core15 .. list-table:: Driver-specific parameters implemented
7 This document describes the devlink features implemented by the ``ionic``15 .. list-table:: devlink info versions implemented
7 This document describes the devlink features implemented by the ``ti-cpsw-switch``16 .. list-table:: Driver-specific parameters implemented
7 This document describes the devlink features implemented by the ``mv88e6xxx``15 .. list-table:: Driver-specific parameters implemented
13 .. list-table:: Generic parameters implemented23 .. list-table:: Driver-specific parameters implemented34 can be implemented.
69 Value of 0xFF indicates that this option is not implemented78 Value of 0xFF indicates that this option is not implemented88 Value of 0xFF indicates that this option is not implemented96 Value of 0xFF indicates that this option is not implemented107 Value of 0xFF indicates that this option is not implemented117 Value of 0xFF indicates that this option is not implemented127 Value of 0xFF indicates that this option is not implemented138 Value of 0xFF indicates that this option is not implemented149 Value of 0xFF indicates that this option is not implemented161 Value of 0xFF indicates that this option is not implemented
8 implemented using ARM specific CPU features or instructions.17 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented27 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented37 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented46 SHA-256 secure hash standard (DFIPS 180-2) implemented54 SHA-256 secure hash standard (DFIPS 180-2) implemented62 SHA-512 secure hash standard (DFIPS 180-2) implemented
33 * CAIF Link Layer, implemented as NET devices.68 each layer described in the specification is implemented as a separate layer.79 specification is implemented in a separate c-file.179 The IP interface and CAIF socket API are implemented on top of the189 The Link Layer is implemented as Linux network devices (struct net_device).194 Therefore a flow-control mechanism is implemented where the physical
35 Supported. Both PEC and block process call support is implemented. Slave36 mode or host notification are not yet implemented.
38 This is implemented using READ_ONCE()/WRITE_ONCE() and47 CPU (A-cumulative property). This is implemented using smp_mb().54 (A-cumulative property). This is implemented using61 after the acquire operation executes. This is implemented using68 Control dependency on stores are not implemented using any explicit
82 * system acoustics optimizations (not implemented)93 * 1 Imon input (not implemented)94 * PECI support (not implemented)95 * 2 GPIO pins (not implemented)96 * system acoustics optimizations (not implemented)
11 This driver is a shim for firmware implemented in ARM's TrustZone19 implemented in firmware. The driver itself doesn't contain much logic and is
31 implemented through a reserved region in BAR4.35 implemented as part of mailbox interface.
4 Cortex-M based processor cores. The NVIC implemented on different SoCs24 - arm,num-irq-priority-bits: The number of priority bits implemented by the
656 cap->implemented = 0; in ceph_add_cap()677 cap->issued = cap->implemented = CEPH_CAP_PIN; in ceph_add_cap()748 cap->implemented |= issued; in ceph_add_cap()787 int __ceph_caps_issued(struct ceph_inode_info *ci, int *implemented) in __ceph_caps_issued() argument793 if (implemented) in __ceph_caps_issued()794 *implemented = 0; in __ceph_caps_issued()802 if (implemented) in __ceph_caps_issued()803 *implemented |= cap->implemented; in __ceph_caps_issued()812 have &= ~cap->implemented | cap->issued; in __ceph_caps_issued()945 (cap->implemented & ~cap->issued & mask)) in __ceph_caps_revoking_other()[all …]