Searched refs:VCS1 (Results 1 – 11 of 11) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 132 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
160 [VCS1] = 0xca00,
347 [VCS1] = 0x4268,
404 [VCS1] = 0xca00, in switch_mocs()
|
| D | execlist.c | 52 [VCS1] = VCS2_AS_CONTEXT_SWITCH,
|
| D | interrupt.c | 582 if (HAS_ENGINE(gvt->gt, VCS1)) { in gen8_init_irq()
|
| D | cmd_parser.c | 425 #define R_VCS2 BIT(VCS1)
639 [VCS1] = {
1165 [VCS1] = {
|
| D | handlers.c | 336 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
2081 id = VCS1; in gvt_reg_tlb_control_handler()
2157 if (HAS_ENGINE(gvt->gt, VCS1)) \
|
| /linux-5.19.10/drivers/gpu/drm/i915/ |
| D | i915_pci.c | 607 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
672 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
754 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
775 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
1039 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
|
| D | intel_gvt_mmio_table.c | 30 if (HAS_ENGINE(to_gt(iter->i915), VCS1)) \
|
| /linux-5.19.10/drivers/gpu/drm/i915/gt/ |
| D | intel_engine_types.h | 111 VCS1, enumerator
|
| D | intel_engine_cs.c | 83 [VCS1] = {
338 [VCS1] = GEN11_GRDOM_MEDIA2, in get_reset_domain()
362 [VCS1] = GEN8_GRDOM_MEDIA2, in get_reset_domain()
1355 [VCS1] = MSG_IDLE_VCS1, in __cs_pending_mi_force_wakes()
|
| D | intel_mocs.c | 542 [VCS1] = __GEN9_VCS1_MOCS0, in mocs_offset()
|
| D | intel_execlists_submission.c | 3477 [VCS1] = GEN8_VCS1_IRQ_SHIFT, in logical_ring_default_irqs()
|