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Searched refs:PcieLaneCount (Results 1 – 25 of 29) sorted by relevance

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/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu9_driver_if.h237 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
Dsmu7_discrete.h212 uint8_t PcieLaneCount; member
Dsmu71_discrete.h154 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
Dsmu11_driver_if.h453 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
Dsmu73_discrete.h130 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
Dsmu74_discrete.h158 uint8_t PcieLaneCount; member
Dsmu72_discrete.h145 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
Dsmu75_discrete.h168 uint8_t PcieLaneCount; member
/linux-5.19.10/drivers/gpu/drm/radeon/
Dsmu7_discrete.h212 uint8_t PcieLaneCount; member
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c524 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : in vega12_override_pcie_parameters()
525 pp_table->PcieLaneCount[i]; in vega12_override_pcie_parameters()
528 pp_table->PcieLaneCount[i]) { in vega12_override_pcie_parameters()
540 pp_table->PcieLaneCount[i] = pcie_width_arg; in vega12_override_pcie_parameters()
555 pp_table->PcieLaneCount[i] = pcie_width; in vega12_override_pcie_parameters()
Dvega20_hwmgr.c869 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : in vega20_override_pcie_parameters()
870 pp_table->PcieLaneCount[i]; in vega20_override_pcie_parameters()
873 pp_table->PcieLaneCount[i]) { in vega20_override_pcie_parameters()
885 pp_table->PcieLaneCount[i] = pcie_width_arg; in vega20_override_pcie_parameters()
900 pp_table->PcieLaneCount[i] = pcie_width; in vega20_override_pcie_parameters()
3461 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
Dvega10_hwmgr.c1545 if (pp_table->PcieLaneCount[i] > pcie_width) in vega10_override_pcie_parameters()
1546 pp_table->PcieLaneCount[i] = pcie_width; in vega10_override_pcie_parameters()
1552 pp_table->PcieLaneCount[i] = pcie_width; in vega10_override_pcie_parameters()
1570 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; in vega10_populate_smc_link_levels()
1583 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; in vega10_populate_smc_link_levels()
4711 lane_width = pptable->PcieLaneCount[i]; in vega10_emit_clock_levels()
4847 lane_width = pptable->PcieLaneCount[i]; in vega10_print_clock_levels()
Dvega20_processpptables.c404 pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
Dsmu9_driver_if.h341 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_sienna_cichlid.h756 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
1115 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
Dsmu11_driver_if_navi10.h626 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
Dsmu13_driver_if_v13_0_0.h1085 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
Dsmu13_driver_if_v13_0_7.h1107 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0_7_ppt.c629 !skutable->PcieLaneCount[link_level] && in smu_v13_0_7_set_default_dpm_table()
636 skutable->PcieLaneCount[link_level]; in smu_v13_0_7_set_default_dpm_table()
Dsmu_v13_0_0_ppt.c606 !skutable->PcieLaneCount[link_level] && in smu_v13_0_0_set_default_dpm_table()
613 skutable->PcieLaneCount[link_level]; in smu_v13_0_0_set_default_dpm_table()
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c2382 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; in navi10_update_pcie_parameters()
2388 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? in navi10_update_pcie_parameters()
2389 pptable->PcieLaneCount[i] : pcie_width_cap); in navi10_update_pcie_parameters()
2400 if (pptable->PcieLaneCount[i] > pcie_width_cap) in navi10_update_pcie_parameters()
Dsienna_cichlid_ppt.c2061 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); in sienna_cichlid_update_pcie_parameters()
2771 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); in beige_goby_dump_pptable()
3409 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); in sienna_cichlid_dump_pptable()
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c583 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in vegam_populate_smc_link_level()
Dfiji_smumgr.c839 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in fiji_populate_smc_link_level()
Diceland_smumgr.c775 table->LinkLevel[i].PcieLaneCount = in iceland_populate_smc_link_level()

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