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/linux-3.4.99/drivers/gpu/drm/radeon/
Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
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Dr100d.h80 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
81 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
83 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
84 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
86 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
87 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
89 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
90 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
92 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
93 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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Drv515d.h221 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
222 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
224 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
225 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
227 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
228 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
230 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
231 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
233 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
234 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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Drs690d.h33 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
34 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
36 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
37 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
40 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
41 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
44 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
45 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
48 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
49 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) argument
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Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
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Dr300d.h81 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
82 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
84 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
85 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
88 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
89 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
91 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
92 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
95 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
96 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
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Dr600d.h67 #define BACKEND_DISABLE(x) ((x) << 16) argument
82 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) argument
83 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) argument
85 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) argument
86 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) argument
96 # define CB_FORMAT(x) ((x) << 2) argument
97 # define CB_ARRAY_MODE(x) ((x) << 8) argument
98 # define CB_SOURCE_FORMAT(x) ((x) << 27) argument
160 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) argument
161 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) argument
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Dr520d.h33 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
34 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
38 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) argument
41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
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Drs400d.h33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
34 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
36 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
37 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
40 #define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
41 #define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
43 #define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
44 #define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
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Drv250d.h32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument
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Devergreend.h46 #define INSTANCE_INDEX(x) ((x) << 0) argument
47 #define SE_INDEX(x) ((x) << 16) argument
54 #define BACKEND_DISABLE(x) ((x) << 16) argument
56 #define NUM_PIPES(x) ((x) << 0) argument
57 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
58 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) argument
59 #define NUM_SHADER_ENGINES(x) ((x) << 12) argument
60 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) argument
61 #define NUM_GPUS(x) ((x) << 20) argument
62 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) argument
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Drv770d.h54 #define BACKEND_DISABLE(x) ((x) << 16) argument
71 #define STQ_SPLIT(x) ((x) << 0) argument
76 #define ROQ_IB1_START(x) ((x) << 0) argument
77 #define ROQ_IB2_START(x) ((x) << 8) argument
79 #define RB_BUFSZ(x) ((x) << 0) argument
80 #define RB_BLKSZ(x) ((x) << 8) argument
95 #define DB_CLK_OFF_DELAY(x) ((x) << 11) argument
100 #define PIPE_TILING(x) ((x) << 1) argument
101 #define BANK_TILING(x) ((x) << 4) argument
102 #define GROUP_SIZE(x) ((x) << 6) argument
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/linux-3.4.99/drivers/net/ethernet/chelsio/cxgb/
Dregs.h46 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
50 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
54 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
58 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
62 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
66 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
71 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
72 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
75 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
79 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
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/linux-3.4.99/drivers/net/ethernet/chelsio/cxgb3/
Dregs.h4 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
8 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument
12 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) argument
16 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
20 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) argument
25 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) argument
29 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) argument
32 #define V_FLMODE(x) ((x) << S_FLMODE) argument
37 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) argument
40 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) argument
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Dsge_defs.h10 #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) argument
11 #define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS) argument
14 #define V_EC_GTS(x) ((x) << S_EC_GTS) argument
19 #define V_EC_INDEX(x) ((x) << S_EC_INDEX) argument
20 #define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX) argument
24 #define V_EC_SIZE(x) ((x) << S_EC_SIZE) argument
25 #define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE) argument
29 #define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO) argument
30 #define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO) argument
34 #define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI) argument
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Dt3_cpl.h190 #define V_OPCODE(x) ((x) << S_OPCODE) argument
191 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) argument
192 #define G_TID(x) ((x) & 0xFFFFFF) argument
195 #define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) argument
199 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) argument
247 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) argument
248 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) argument
252 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) argument
253 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) argument
257 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) argument
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/linux-3.4.99/drivers/infiniband/hw/cxgb3/
Dtcb.h38 #define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) argument
43 #define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) argument
48 #define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) argument
53 #define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) argument
58 #define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) argument
63 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) argument
68 #define V_TCB_TOS(x) ((x) << S_TCB_TOS) argument
73 #define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) argument
78 #define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) argument
83 #define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) argument
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/linux-3.4.99/drivers/staging/rtl8712/
Dbig_endian.h38 #define __constant_htonl(x) ((__u32)(x)) argument
39 #define __constant_ntohl(x) ((__u32)(x)) argument
40 #define __constant_htons(x) ((__u16)(x)) argument
41 #define __constant_ntohs(x) ((__u16)(x)) argument
42 #define __constant_cpu_to_le64(x) ___constant_swab64((x)) argument
43 #define __constant_le64_to_cpu(x) ___constant_swab64((x)) argument
44 #define __constant_cpu_to_le32(x) ___constant_swab32((x)) argument
45 #define __constant_le32_to_cpu(x) ___constant_swab32((x)) argument
46 #define __constant_cpu_to_le16(x) ___constant_swab16((x)) argument
47 #define __constant_le16_to_cpu(x) ___constant_swab16((x)) argument
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Dlittle_endian.h38 #define __constant_htonl(x) ___constant_swab32((x)) argument
39 #define __constant_ntohl(x) ___constant_swab32((x)) argument
40 #define __constant_htons(x) ___constant_swab16((x)) argument
41 #define __constant_ntohs(x) ___constant_swab16((x)) argument
42 #define __constant_cpu_to_le64(x) ((__u64)(x)) argument
43 #define __constant_le64_to_cpu(x) ((__u64)(x)) argument
44 #define __constant_cpu_to_le32(x) ((__u32)(x)) argument
45 #define __constant_le32_to_cpu(x) ((__u32)(x)) argument
46 #define __constant_cpu_to_le16(x) ((__u16)(x)) argument
47 #define __constant_le16_to_cpu(x) ((__u16)(x)) argument
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/linux-3.4.99/arch/m68k/include/asm/
Dm532xsim.h18 #define MCF_REG32(x) (*(volatile unsigned long *)(x)) argument
19 #define MCF_REG16(x) (*(volatile unsigned short *)(x)) argument
20 #define MCF_REG08(x) (*(volatile unsigned char *)(x)) argument
152 #define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) argument
154 #define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F)) argument
215 #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) argument
218 #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) argument
224 #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) argument
227 #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) argument
230 #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) argument
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/linux-3.4.99/drivers/net/ethernet/chelsio/cxgb4/
Dt4fw_api.h70 #define FW_WR_OP(x) ((x) << 24) argument
71 #define FW_WR_ATOMIC(x) ((x) << 23) argument
72 #define FW_WR_FLUSH(x) ((x) << 22) argument
73 #define FW_WR_COMPL(x) ((x) << 21) argument
75 #define FW_WR_IMMDLEN(x) ((x) << 0) argument
79 #define FW_WR_FLOWID(x) ((x) << 8) argument
80 #define FW_WR_LEN16(x) ((x) << 0) argument
119 #define FW_FLOWC_WR_NPARAMS(x) ((x) << 0) argument
129 #define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19) argument
130 #define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18) argument
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/linux-3.4.99/drivers/video/exynos/
Dexynos_mipi_dsi_regs.h48 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) argument
57 #define DSIM_LPDR_TOUT_SHIFT(x) ((x) << 0) argument
58 #define DSIM_BTA_TOUT_SHIFT(x) ((x) << 16) argument
61 #define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << 19) argument
62 #define DSIM_BYTE_CLKEN_SHIFT(x) ((x) << 24) argument
63 #define DSIM_BYTE_CLK_SRC_SHIFT(x) ((x) << 25) argument
64 #define DSIM_PLL_BYPASS_SHIFT(x) ((x) << 27) argument
65 #define DSIM_ESC_CLKEN_SHIFT(x) ((x) << 28) argument
66 #define DSIM_TX_REQUEST_HSCLK_SHIFT(x) ((x) << 31) argument
69 #define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0) argument
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/linux-3.4.99/arch/mips/include/asm/sibyte/
Dbcm1480_mc.h44 #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) argument
45 #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV… argument
50 #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) argument
51 #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV… argument
56 #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) argument
57 #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV… argument
62 #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) argument
63 #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_M… argument
85 #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) argument
86 #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS… argument
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Dsb1250_genbus.h53 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
58 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) argument
59 #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) argument
63 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
75 #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) argument
76 #define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) argument
84 #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) argument
85 #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) argument
95 #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) argument
96 #define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) argument
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/linux-3.4.99/drivers/infiniband/hw/cxgb4/
Dt4fw_ri_api.h167 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) argument
168 #define G_FW_RI_TPTE_VALID(x) \ argument
169 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
174 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) argument
175 #define G_FW_RI_TPTE_STAGKEY(x) \ argument
176 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
180 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) argument
181 #define G_FW_RI_TPTE_STAGSTATE(x) \ argument
182 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
187 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) argument
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