Searched refs:uint32_t (Results 1 – 25 of 1166) sorted by relevance
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59 uint32_t host_status;60 uint32_t host_reg[32];61 uint32_t shadow_reg[7];63 uint32_t xseq_gp_reg[128];64 uint32_t xseq_0_reg[16];65 uint32_t xseq_1_reg[16];66 uint32_t rseq_gp_reg[128];67 uint32_t rseq_0_reg[16];68 uint32_t rseq_1_reg[16];69 uint32_t rseq_2_reg[16];[all …]
187 uint32_t u32;189 uint32_t devid:16;190 uint32_t vendid:16;199 uint32_t u32;201 uint32_t dpe:1;202 uint32_t sse:1;203 uint32_t rma:1;204 uint32_t rta:1;205 uint32_t sta:1;206 uint32_t devt:2;[all …]
110 uint32_t u32;112 uint32_t devid:16;113 uint32_t vendid:16;128 uint32_t u32;130 uint32_t dpe:1;131 uint32_t sse:1;132 uint32_t rma:1;133 uint32_t rta:1;134 uint32_t sta:1;135 uint32_t devt:2;[all …]
118 uint32_t u32;120 uint32_t reserved_18_31:14;121 uint32_t addr_idx:14;122 uint32_t ca:1;123 uint32_t end_swp:2;124 uint32_t addr_v:1;154 uint32_t u32;156 uint32_t devid:16;157 uint32_t vendid:16;169 uint32_t u32;[all …]
14 uint32_t timestamp;17 uint32_t zero:24;18 uint32_t phy_id:6;19 uint32_t identifier:2;23 uint32_t zero:16;24 uint32_t gap_count:6;25 uint32_t set_gap_count:1;26 uint32_t set_root:1;27 uint32_t root_id:6;28 uint32_t identifier:2;[all …]
79 uint32_t Revision:8;80 uint32_t InId:24;82 uint32_t word;88 uint32_t CmdRsp:16;89 uint32_t Size:16;91 uint32_t word;111 uint32_t PortID;119 uint32_t PortId; /* For RFT_ID requests */122 uint32_t rsvd0:16;123 uint32_t rsvd1:7;[all …]
80 #define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))81 #define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))106 uint32_t buffer_tag; /* used for tagged queue ring */111 uint32_t max_count;112 uint32_t current_count;118 uint32_t size;119 uint32_t tag;132 uint32_t status; /* vpd status value */133 uint32_t length; /* number of bytes actually returned */135 uint32_t rsvd1; /* Revision numbers */[all …]
40 uint32_t command;41 uint32_t type_mask;42 uint32_t ev_req_id;43 uint32_t ev_reg_id;47 uint32_t command;48 uint32_t ev_reg_id;49 uint32_t ev_req_id;53 uint32_t immed_data;54 uint32_t type;58 uint32_t command;[all …]
59 uint32_t addr_lo;60 uint32_t addr_hi;64 uint32_t word0;201 uint32_t w;204 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED206 uint32_t bdeSize:24; /* Size of buffer (in bytes) */208 uint32_t bdeSize:24; /* Size of buffer (in bytes) */209 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED221 uint32_t addrLow;222 uint32_t addrHigh;[all …]
82 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)83 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)91 uint32_t HeaderLength;93 uint32_t Timeout;94 uint32_t ControlCode;95 uint32_t ReturnCode;96 uint32_t Length;173 uint32_t data_len;183 uint32_t signature; /*0, 00-03*/184 uint32_t request_len; /*1, 04-07*/[all …]
286 uint32_t saveDSPACNTR;287 uint32_t saveDSPBCNTR;288 uint32_t savePIPEACONF;289 uint32_t savePIPEBCONF;290 uint32_t savePIPEASRC;291 uint32_t savePIPEBSRC;292 uint32_t saveFPA0;293 uint32_t saveFPA1;294 uint32_t saveDPLL_A;295 uint32_t saveDPLL_A_MD;[all …]
90 uint32_t param;91 uint32_t pad64;113 uint32_t pad64;155 uint32_t flags;156 uint32_t format;157 uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];175 uint32_t pad64;190 uint32_t width;191 uint32_t height;192 uint32_t depth;[all …]
31 uint32_t fb_ctxdma_handle;32 uint32_t tt_ctxdma_handle;35 uint32_t pushbuf_domains;38 uint32_t notifier_handle;42 uint32_t handle;43 uint32_t grclass;45 uint32_t nr_subchan;54 uint32_t handle;59 uint32_t channel;60 uint32_t handle;[all …]
113 uint32_t low_part;114 uint32_t high_part;123 uint32_t mask_tx_done:1;124 uint32_t mask_tx_err:1;125 uint32_t mask_rx_done:1;126 uint32_t mask_rx_err:1;127 uint32_t mask_pcie_err:1;128 uint32_t mask_pcie_rbusmast_err:1;129 uint32_t mask_pcie_rgr_bridge:1;130 uint32_t reserved:25;[all …]
35 uint32_t type;36 uint32_t size;43 uint32_t to_be_defined;44 uint32_t valid;48 uint32_t display_horizontal_size;49 uint32_t display_vertical_size;53 uint32_t offset_count;69 uint32_t to_be_defined;70 uint32_t valid;74 uint32_t display_horizontal_size;[all …]
73 uint32_t Offset;74 uint32_t Value;78 uint32_t StartOff;79 uint32_t NumDwords;80 uint32_t Rsrd;90 uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ];91 uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ];92 uint32_t flags;93 uint32_t add_data;104 uint32_t Size;[all …]
43 extern uint32_t g_linklog_level;66 uint32_t xfr_len;67 uint32_t uv_offset;70 uint32_t uv_sg_ix;71 uint32_t uv_sg_off;74 uint32_t y_done_sz;75 uint32_t uv_done_sz;76 uint32_t comp_flags;81 uint32_t sig;82 uint32_t max_pages;[all …]
53 uint32_t cmd;54 uint32_t addr;55 uint32_t val;59 uint32_t cmd;60 uint32_t cntxt_type;61 uint32_t cntxt_id;62 uint32_t data[4];69 uint32_t cmd;70 uint32_t queue_num;71 uint32_t idx;[all …]
96 uint32_t type; /* k/u events type */97 uint32_t iferror; /* carries interface or resource errors */103 uint32_t initial_cmdsn;109 uint32_t initial_cmdsn;114 uint32_t sid;117 uint32_t sid;118 uint32_t cid;121 uint32_t sid;122 uint32_t cid;124 uint32_t is_leading;[all …]
33 uint32_t ChipId; /* Chip ID */34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */35 uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */36 uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */37 uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */38 uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */39 uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */40 uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */41 uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */42 uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */[all …]
14 volatile uint32_t ctrlstat; /* general control */15 volatile uint32_t dotclock; /* dot clock PLL control */16 volatile uint32_t i2c; /* crt I2C control */17 volatile uint32_t sysclk; /* system clock PLL control */18 volatile uint32_t i2cfp; /* flat panel I2C control */19 volatile uint32_t id; /* device id/chip revision */20 volatile uint32_t config; /* power on configuration [1] */21 volatile uint32_t bist; /* internal bist status [1] */22 uint32_t _pad0[0x010000/4 - 8];23 volatile uint32_t vt_xy; /* current dot coords */[all …]
97 uint32_t ioc_number;98 uint32_t port_number;99 uint32_t max_data_size;121 uint32_t device:5;122 uint32_t function:3;123 uint32_t bus:24;125 uint32_t word;127 uint32_t segment_id;159 uint32_t adapter_type;160 uint32_t port_number;[all …]
34 uint32_t raw;36 uint32_t valid:1; /* Address captured */37 uint32_t master_id:4; /* Unit causing error45 uint32_t mul_err:1; /* Multiple errors occurred */46 uint32_t addr:26; /* Bits 31-6 of error addr */49 uint32_t pci_err_addr_h; /* Bits 63-32 of error addr */51 uint32_t raw;64 uint32_t raw;66 uint32_t ata_int:1; /* ATA port passthru */67 uint32_t ata_memerr:1; /* ATA halted by mem error */[all …]
41 uint32_t secs;42 uint32_t nsecs;59 uint32_t type;61 uint32_t handle;62 uint32_t reg;76 uint32_t handle;77 uint32_t reg;85 uint32_t reg;89 uint32_t type;97 uint32_t length; /* Length of microcode data. */[all …]
42 volatile uint32_t nothing; /* reg 0 */43 volatile uint32_t io_eim;44 volatile uint32_t io_dc_adata;45 volatile uint32_t io_ii_cdata;46 volatile uint32_t io_dma_link; /* reg 4 */47 volatile uint32_t io_dma_command;48 volatile uint32_t io_dma_address;49 volatile uint32_t io_dma_count;50 volatile uint32_t io_flex; /* reg 8 */51 volatile uint32_t io_spa_address;[all …]