Searched refs:pmc_readl (Results 1 – 3 of 3) sorted by relevance
373 #define pmc_readl(reg) \ macro735 val = pmc_readl(PMC_CTRL); in tegra30_blink_clk_init()738 val = pmc_readl(c->reg); in tegra30_blink_clk_init()759 val = pmc_readl(PMC_DPD_PADS_ORIDE); in tegra30_blink_clk_enable()762 val = pmc_readl(PMC_CTRL); in tegra30_blink_clk_enable()772 val = pmc_readl(PMC_CTRL); in tegra30_blink_clk_disable()775 val = pmc_readl(PMC_DPD_PADS_ORIDE); in tegra30_blink_clk_disable()945 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); in tegra30_pll_clk_enable()965 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); in tegra30_pll_clk_disable()1184 val = pmc_readl(PMC_SATA_PWRGT); in tegra30_plle_training()[all …]
174 #define pmc_readl(reg) \ macro533 val = pmc_readl(PMC_CTRL); in tegra2_blink_clk_init()536 val = pmc_readl(c->reg); in tegra2_blink_clk_init()557 val = pmc_readl(PMC_DPD_PADS_ORIDE); in tegra2_blink_clk_enable()560 val = pmc_readl(PMC_CTRL); in tegra2_blink_clk_enable()570 val = pmc_readl(PMC_CTRL); in tegra2_blink_clk_disable()573 val = pmc_readl(PMC_DPD_PADS_ORIDE); in tegra2_blink_clk_disable()
156 #define pmc_readl(reg) \ macro687 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; in tegra_pcie_xclk_clamp()