Searched refs:divu71 (Results 1 – 2 of 2) sorted by relevance
763 u32 divu71; in tegra2_pll_div_clk_init() local770 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; in tegra2_pll_div_clk_init()771 c->div = (divu71 + 2); in tegra2_pll_div_clk_init()924 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; in tegra2_periph_clk_init() local925 c->div = divu71 + 2; in tegra2_periph_clk_init()
1271 u32 divu71; in tegra30_pll_div_clk_init() local1278 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; in tegra30_pll_div_clk_init()1279 c->div = (divu71 + 2); in tegra30_pll_div_clk_init()1445 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; in tegra30_periph_clk_init() local1448 divu71 = 0; in tegra30_periph_clk_init()1457 c->div = divu71 + 2; in tegra30_periph_clk_init()