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Searched refs:divu71 (Results 1 – 2 of 2) sorted by relevance

/linux-3.4.99/arch/arm/mach-tegra/
Dtegra2_clocks.c763 u32 divu71; in tegra2_pll_div_clk_init() local
770 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; in tegra2_pll_div_clk_init()
771 c->div = (divu71 + 2); in tegra2_pll_div_clk_init()
924 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; in tegra2_periph_clk_init() local
925 c->div = divu71 + 2; in tegra2_periph_clk_init()
Dtegra30_clocks.c1271 u32 divu71; in tegra30_pll_div_clk_init() local
1278 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; in tegra30_pll_div_clk_init()
1279 c->div = (divu71 + 2); in tegra30_pll_div_clk_init()
1445 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; in tegra30_periph_clk_init() local
1448 divu71 = 0; in tegra30_periph_clk_init()
1457 c->div = divu71 + 2; in tegra30_periph_clk_init()