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Searched refs:__raw_writel (Results 1 – 25 of 734) sorted by relevance

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/linux-3.4.99/arch/arm/mach-iop13xx/
Dpci.c252 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, in iop13xx_atux_pci_status()
288 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atux_read_config()
317 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
319 __raw_writel(addr, IOP13XX_ATUX_OCCAR); in iop13xx_atux_write_config()
320 __raw_writel(value, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
384 __raw_writel(status, IOP13XX_ATUE_PIE_STS); in iop13xx_atue_pci_status()
409 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_read()
431 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atue_read_config()
464 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); in iop13xx_atue_write_config()
466 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_write_config()
[all …]
/linux-3.4.99/arch/mips/kernel/
Dcevt-txx9.c57 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
58 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
59 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
60 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
61 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
62 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
74 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
76 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
89 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, in txx9tmr_set_mode()
92 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> in txx9tmr_set_mode()
[all …]
Dirq_txx9.c72 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_unmask()
77 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_unmask()
78 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_unmask()
88 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_mask()
93 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_mask()
94 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_mask()
109 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr); in txx9_irq_mask_ack()
135 __raw_writel(cr, crp); in txx9_irq_set_type()
162 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_init()
164 __raw_writel(0, &txx9_ircptr->ilr[i]); in txx9_irq_init()
[all …]
/linux-3.4.99/arch/mips/alchemy/common/
Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_ack()
[all …]
Dvss.c26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
33 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
35 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
37 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
39 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
57 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ in __disable_block()
[all …]
/linux-3.4.99/arch/arm/mach-mmp/
Dtime.c51 __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1)); in timer_read()
71 __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0)); in timer_interrupt()
76 __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER); in timer_interrupt()
93 __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER); in timer_set_next_event()
98 __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0)); in timer_set_next_event()
99 __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0)); in timer_set_next_event()
104 __raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0)); in timer_set_next_event()
109 __raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER); in timer_set_next_event()
127 __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0)); in timer_set_mode()
162 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */ in timer_config()
[all …]
/linux-3.4.99/arch/arm/mach-pnx4008/
Dtime.c63 __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH, in pnx4008_timer_interrupt()
65 __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */ in pnx4008_timer_interrupt()
91 __raw_writel(RESET_COUNT, MSTIM_CTRL); in pnx4008_setup_timer()
93 __raw_writel(0, MSTIM_CTRL); /* stop the timer */ in pnx4008_setup_timer()
94 __raw_writel(0, MSTIM_MCTRL); in pnx4008_setup_timer()
96 __raw_writel(RESET_COUNT, HSTIM_CTRL); in pnx4008_setup_timer()
98 __raw_writel(0, HSTIM_CTRL); in pnx4008_setup_timer()
99 __raw_writel(0, HSTIM_MCTRL); in pnx4008_setup_timer()
100 __raw_writel(0, HSTIM_CCR); in pnx4008_setup_timer()
101 __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */ in pnx4008_setup_timer()
[all …]
Dirq.c40 …__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt… in pnx4008_mask_irq()
45 …__raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrup… in pnx4008_unmask_irq()
50 …__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt… in pnx4008_mask_ack_irq()
51 __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */ in pnx4008_mask_ack_irq()
58 …__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive… in pnx4008_set_irq_type()
59 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ in pnx4008_set_irq_type()
63 …__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive… in pnx4008_set_irq_type()
64 …__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge … in pnx4008_set_irq_type()
68 …__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensiti… in pnx4008_set_irq_type()
69 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ in pnx4008_set_irq_type()
[all …]
/linux-3.4.99/arch/mips/sgi-ip22/
Dip22-nvram.c35 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
36 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
39 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
44 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
46 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
63 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/linux-3.4.99/drivers/usb/host/
Dalchemy-common.c109 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
115 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
125 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
131 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
138 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
142 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
147 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
153 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
167 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
172 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
[all …]
/linux-3.4.99/arch/arm/mach-lpc32xx/
Dtimer.c37 __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, in lpc32xx_clkevt_next_event()
39 __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); in lpc32xx_clkevt_next_event()
40 __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN, in lpc32xx_clkevt_next_event()
61 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); in lpc32xx_clkevt_mode()
84 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), in lpc32xx_timer_interrupt()
108 __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN | in lpc32xx_timer_init()
131 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); in lpc32xx_timer_init()
132 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), in lpc32xx_timer_init()
134 __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); in lpc32xx_timer_init()
135 __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) | in lpc32xx_timer_init()
[all …]
Dirq.c209 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); in lpc32xx_mask_irq()
219 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); in lpc32xx_unmask_irq()
228 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); in lpc32xx_ack_irq()
232 __raw_writel(lpc32xx_events[d->irq].mask, in lpc32xx_ack_irq()
249 __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl)); in __lpc32xx_set_irq_type()
257 __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl)); in __lpc32xx_set_irq_type()
268 __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg); in __lpc32xx_set_irq_type()
323 __raw_writel(lpc32xx_events[d->irq].mask, in lpc32xx_irq_wake()
328 __raw_writel(eventreg, in lpc32xx_irq_wake()
335 __raw_writel(lpc32xx_events[d->irq].mask, in lpc32xx_irq_wake()
[all …]
/linux-3.4.99/arch/arm/mach-s3c24xx/
Dmach-n30.c408 __raw_writel(0x007fffff, S3C2410_GPACON); in n30_hwinit()
410 __raw_writel(0x007fefff, S3C2410_GPACON); in n30_hwinit()
411 __raw_writel(0x00000000, S3C2410_GPADAT); in n30_hwinit()
426 __raw_writel(0x00154556, S3C2410_GPBCON); in n30_hwinit()
427 __raw_writel(0x00000750, S3C2410_GPBDAT); in n30_hwinit()
428 __raw_writel(0x00000073, S3C2410_GPBUP); in n30_hwinit()
445 __raw_writel(0xaaa80618, S3C2410_GPCCON); in n30_hwinit()
446 __raw_writel(0x0000014c, S3C2410_GPCDAT); in n30_hwinit()
447 __raw_writel(0x0000fef2, S3C2410_GPCUP); in n30_hwinit()
457 __raw_writel(0xaa95aaa4, S3C2410_GPDCON); in n30_hwinit()
[all …]
Dirq-s3c2412.c58 __raw_writel(mask | bitval, S3C2410_INTMSK); in s3c2412_irq_mask()
61 __raw_writel(mask | bitval, S3C2412_EINTMASK); in s3c2412_irq_mask()
69 __raw_writel(bitval, S3C2412_EINTPEND); in s3c2412_irq_ack()
70 __raw_writel(bitval, S3C2410_SRCPND); in s3c2412_irq_ack()
71 __raw_writel(bitval, S3C2410_INTPND); in s3c2412_irq_ack()
81 __raw_writel(mask|bitval, S3C2410_INTMSK); in s3c2412_irq_maskack()
84 __raw_writel(mask | bitval, S3C2412_EINTMASK); in s3c2412_irq_maskack()
86 __raw_writel(bitval, S3C2412_EINTPEND); in s3c2412_irq_maskack()
87 __raw_writel(bitval, S3C2410_SRCPND); in s3c2412_irq_maskack()
88 __raw_writel(bitval, S3C2410_INTPND); in s3c2412_irq_maskack()
[all …]
/linux-3.4.99/arch/arm/mach-at91/
Dgpio.c148 __raw_writel(mask, pio + PIO_IDR); in at91_set_GPIO_periph()
149 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); in at91_set_GPIO_periph()
150 __raw_writel(mask, pio + PIO_PER); in at91_set_GPIO_periph()
167 __raw_writel(mask, pio + PIO_IDR); in at91_set_A_periph()
168 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); in at91_set_A_periph()
170 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, in at91_set_A_periph()
172 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, in at91_set_A_periph()
175 __raw_writel(mask, pio + PIO_ASR); in at91_set_A_periph()
177 __raw_writel(mask, pio + PIO_PDR); in at91_set_A_periph()
194 __raw_writel(mask, pio + PIO_IDR); in at91_set_B_periph()
[all …]
/linux-3.4.99/drivers/clocksource/
Dtcb_clksrc.c101 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR)); in tc_mode()
102 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_mode()
115 __raw_writel(timer_clock in tc_mode()
118 __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); in tc_mode()
121 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); in tc_mode()
124 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, in tc_mode()
132 __raw_writel(timer_clock | ATMEL_TC_CPCSTOP in tc_mode()
135 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); in tc_mode()
147 __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC)); in tc_next_event()
150 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, in tc_next_event()
[all …]
/linux-3.4.99/arch/mips/pci/
Dops-tx4927.c68 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
73 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
88 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
134 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
242 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
250 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
264 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
269 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
284 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
287 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
[all …]
/linux-3.4.99/arch/arm/mach-pxa/
Dsmemc.c35 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
36 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
37 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
38 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
39 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
40 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
44 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
63 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
/linux-3.4.99/arch/sh/drivers/pci/
Dpci-sh7780.c130 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
143 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
157 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
172 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
203 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
208 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
234 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
244 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
261 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
264 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS, in sh7780_pci_init()
[all …]
/linux-3.4.99/arch/sh/mm/
Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
/linux-3.4.99/arch/arm/plat-samsung/include/plat/
Dirq.h43 __raw_writel(mask | parentbit, S3C2410_INTMSK); in s3c_irqsub_mask()
46 __raw_writel(submask, S3C2410_INTSUBMSK); in s3c_irqsub_mask()
63 __raw_writel(submask, S3C2410_INTSUBMSK); in s3c_irqsub_unmask()
64 __raw_writel(mask, S3C2410_INTMSK); in s3c_irqsub_unmask()
76 __raw_writel(bit, S3C2410_SUBSRCPND); in s3c_irqsub_maskack()
84 __raw_writel(parentmask, S3C2410_SRCPND); in s3c_irqsub_maskack()
85 __raw_writel(parentmask, S3C2410_INTPND); in s3c_irqsub_maskack()
95 __raw_writel(bit, S3C2410_SUBSRCPND); in s3c_irqsub_ack()
103 __raw_writel(parentmask, S3C2410_SRCPND); in s3c_irqsub_ack()
104 __raw_writel(parentmask, S3C2410_INTPND); in s3c_irqsub_ack()
/linux-3.4.99/arch/sh/kernel/cpu/sh4a/
Dubc.c37 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
38 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
43 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
44 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
53 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
62 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
85 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
115 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
118 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
119 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
/linux-3.4.99/arch/arm/common/
Dit8152.c40 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | in it8152_mask_irq()
44 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | in it8152_mask_irq()
48 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | in it8152_mask_irq()
59 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & in it8152_unmask_irq()
63 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & in it8152_unmask_irq()
67 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & in it8152_unmask_irq()
84 __raw_writel((0xffff), IT8152_INTC_PDCNIMR); in it8152_init_irq()
85 __raw_writel((0), IT8152_INTC_PDCNIRR); in it8152_init_irq()
86 __raw_writel((0xffff), IT8152_INTC_LPCNIMR); in it8152_init_irq()
87 __raw_writel((0), IT8152_INTC_LPCNIRR); in it8152_init_irq()
[all …]
/linux-3.4.99/arch/arm/mach-ks8695/
Dpci.c55 __raw_writel(pbca, KS8695_PCI_VA + KS8695_PBCA); in ks8695_pci_setupconfig()
58 __raw_writel(pbca | PBCA_TYPE1, KS8695_PCI_VA + KS8695_PBCA); in ks8695_pci_setupconfig()
112 __raw_writel(value, KS8695_PCI_VA + KS8695_PBCD); in ks8695_pci_writeconfig()
119 __raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD); in ks8695_pci_writeconfig()
126 __raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD); in ks8695_pci_writeconfig()
136 __raw_writel(value, KS8695_PCI_VA + KS8695_PBCD); in ks8695_local_writeconfig()
215 __raw_writel(cmdstat, KS8695_PCI_VA + KS8695_CRCFCS); in ks8695_pci_fault()
249 __raw_writel(0x80000000, KS8695_PCI_VA + KS8695_PBCS); in ks8695_pci_preinit()
252 __raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID); in ks8695_pci_preinit()
256 __raw_writel(0x40000000, KS8695_PCI_VA + KS8695_PBCS); in ks8695_pci_preinit()
[all …]
/linux-3.4.99/arch/arm/plat-mxc/
Dcpu.c30 __raw_writel(0x77777777, base + 0x0); in imx_set_aips()
31 __raw_writel(0x77777777, base + 0x4); in imx_set_aips()
38 __raw_writel(0x0, base + 0x40); in imx_set_aips()
39 __raw_writel(0x0, base + 0x44); in imx_set_aips()
40 __raw_writel(0x0, base + 0x48); in imx_set_aips()
41 __raw_writel(0x0, base + 0x4C); in imx_set_aips()
43 __raw_writel(reg, base + 0x50); in imx_set_aips()

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