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/linux-3.4.99/arch/ia64/kernel/
Dperfmon_itanium.h11 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
15 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
16 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
17 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
18 … */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
19 …REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
20 …REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
[all …]
Dperfmon_mckinley.h11 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
15 …00000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
16 …NG, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
17 …NG, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
18 …NG, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
19 …ffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
20 …fffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
[all …]
Dperfmon_generic.h10 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
11 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
15 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
16 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
17 … */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
26 …4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}…
27 …5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}…
[all …]
/linux-3.4.99/arch/sparc/include/asm/
Dpstate.h13 #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
14 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
15 #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
16 #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
17 #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
18 #define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
19 #define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
20 #define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
21 #define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */
22 #define PSTATE_PEF _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
[all …]
Ddcu.h7 #define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
8 #define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
9 #define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
10 #define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
11 #define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
12 #define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
13 #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
14 #define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
15 #define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
16 #define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
[all …]
Dsfafsr.h8 #define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
10 #define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
12 #define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
14 #define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
16 #define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
18 #define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
20 #define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
22 #define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
24 #define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
26 #define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
[all …]
Dpgtable_64.h35 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
36 #define TSBMAP_BASE _AC(0x0000000008000000,UL)
37 #define MODULES_VADDR _AC(0x0000000010000000,UL)
38 #define MODULES_LEN _AC(0x00000000e0000000,UL)
39 #define MODULES_END _AC(0x00000000f0000000,UL)
40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42 #define VMALLOC_START _AC(0x0000000100000000,UL)
43 #define VMALLOC_END _AC(0x0000010000000000,UL)
44 #define VMEMMAP_BASE _AC(0x0000010000000000,UL)
[all …]
Dlsu.h7 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
8 #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
9 #define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
10 #define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
11 #define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
12 #define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
13 #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
14 #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
15 #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
16 #define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
[all …]
Dmmu_64.h10 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
19 #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
21 #define CTX_PGSZ_8KB _AC(0x0,UL)
22 #define CTX_PGSZ_64KB _AC(0x1,UL)
23 #define CTX_PGSZ_512KB _AC(0x2,UL)
24 #define CTX_PGSZ_4MB _AC(0x3,UL)
25 #define CTX_PGSZ_BITS _AC(0x7,UL)
69 #define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
/linux-3.4.99/arch/arm/mach-spear6xx/include/mach/
Dspear.h20 #define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
22 #define SPEAR6XX_ICM1_BASE UL(0xD0000000)
24 #define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
27 #define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
28 #define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
29 #define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
30 #define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
31 #define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
32 #define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
33 #define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
[all …]
/linux-3.4.99/arch/arm/mach-spear3xx/include/mach/
Dspear.h22 #define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
24 #define SPEAR3XX_ICM9_BASE UL(0xC0000000)
27 #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28 #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
30 #define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
31 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
32 #define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
33 #define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
34 #define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
35 #define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
[all …]
Dspear320.h19 #define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20 #define SPEAR320_FSMC_BASE UL(0x4C000000)
21 #define SPEAR320_NAND_BASE UL(0x50000000)
22 #define SPEAR320_I2S_BASE UL(0x60000000)
23 #define SPEAR320_SDHCI_BASE UL(0x70000000)
24 #define SPEAR320_CLCD_BASE UL(0x90000000)
25 #define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26 #define SPEAR320_CAN0_BASE UL(0xA1000000)
27 #define SPEAR320_CAN1_BASE UL(0xA2000000)
28 #define SPEAR320_UART1_BASE UL(0xA3000000)
[all …]
Dspear300.h20 #define SPEAR300_TELECOM_BASE UL(0x50000000)
37 #define SPEAR300_CLCD_BASE UL(0x60000000)
38 #define SPEAR300_SDHCI_BASE UL(0x70000000)
39 #define SPEAR300_NAND_0_BASE UL(0x80000000)
40 #define SPEAR300_NAND_1_BASE UL(0x84000000)
41 #define SPEAR300_NAND_2_BASE UL(0x88000000)
42 #define SPEAR300_NAND_3_BASE UL(0x8c000000)
43 #define SPEAR300_NOR_0_BASE UL(0x90000000)
44 #define SPEAR300_NOR_1_BASE UL(0x91000000)
45 #define SPEAR300_NOR_2_BASE UL(0x92000000)
[all …]
Dspear310.h19 #define SPEAR310_NAND_BASE UL(0x40000000)
20 #define SPEAR310_FSMC_BASE UL(0x44000000)
21 #define SPEAR310_UART1_BASE UL(0xB2000000)
22 #define SPEAR310_UART2_BASE UL(0xB2080000)
23 #define SPEAR310_UART3_BASE UL(0xB2100000)
24 #define SPEAR310_UART4_BASE UL(0xB2180000)
25 #define SPEAR310_UART5_BASE UL(0xB2200000)
26 #define SPEAR310_HDLC_BASE UL(0xB2800000)
27 #define SPEAR310_RS485_0_BASE UL(0xB3000000)
28 #define SPEAR310_RS485_1_BASE UL(0xB3800000)
[all …]
/linux-3.4.99/arch/x86/kernel/cpu/mtrr/
Dcyrix.c242 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
243 {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
/linux-3.4.99/arch/mips/include/asm/mach-generic/
Dspaces.h19 #define PHYS_OFFSET _AC(0, UL)
24 #define CAC_BASE _AC(0x80000000, UL)
25 #define IO_BASE _AC(0xa0000000, UL)
26 #define UNCAC_BASE _AC(0xa0000000, UL)
29 #define MAP_BASE _AC(0xc0000000, UL)
36 #define HIGHMEM_START _AC(0x20000000, UL)
45 #define CAC_BASE _AC(0x9800000000000000, UL)
47 #define CAC_BASE _AC(0xa800000000000000, UL)
52 #define IO_BASE _AC(0x9000000000000000, UL)
56 #define UNCAC_BASE _AC(0x9000000000000000, UL)
[all …]
/linux-3.4.99/arch/x86/include/asm/
Dpgtable_64_types.h47 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
49 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
51 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
55 #define MAXMEM _AC(__AC(1, UL) << MAX_PHYSMEM_BITS, UL)
56 #define VMALLOC_START _AC(0xffffc90000000000, UL)
57 #define VMALLOC_END _AC(0xffffe8ffffffffff, UL)
58 #define VMEMMAP_START _AC(0xffffea0000000000, UL)
59 #define MODULES_VADDR _AC(0xffffffffa0000000, UL)
60 #define MODULES_END _AC(0xffffffffff000000, UL)
/linux-3.4.99/arch/sparc/kernel/
Dtraps_32.c177 { ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
178 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
179 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
180 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL };
/linux-3.4.99/arch/arm/include/asm/
Dmemory.h29 #define UL(x) _AC(x, UL) macro
38 #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
39 #define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000))
40 #define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3)
45 #define TASK_SIZE_26 UL(0x04000000)
98 #define TASK_UNMAPPED_BASE UL(0x00000000)
102 #define PHYS_OFFSET UL(CONFIG_DRAM_BASE)
106 #define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
128 #define ITCM_OFFSET UL(0xfffe0000)
129 #define DTCM_OFFSET UL(0xfffe8000)
[all …]
/linux-3.4.99/lib/
Dfind_next_bit.c36 tmp &= (~0UL << offset); in find_next_bit()
55 tmp &= (~0UL >> (BITS_PER_LONG - size)); in find_next_bit()
56 if (tmp == 0UL) /* Are any bits set? */ in find_next_bit()
82 tmp |= ~0UL >> (BITS_PER_LONG - offset); in find_next_zero_bit()
101 tmp |= ~0UL << size; in find_next_zero_bit()
102 if (tmp == ~0UL) /* Are any bits zero? */ in find_next_zero_bit()
129 tmp = (*p) & (~0UL >> (BITS_PER_LONG - size)); in find_first_bit()
130 if (tmp == 0UL) /* Are any bits set? */ in find_first_bit()
157 tmp = (*p) | (~0UL << size); in find_first_zero_bit()
158 if (tmp == ~0UL) /* Are any bits zero? */ in find_first_zero_bit()
[all …]
/linux-3.4.99/arch/tile/include/asm/
Dpage.h26 #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
27 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
164 #define HALF_VA_SPACE (_AC(1, UL) << (CHIP_VA_WIDTH() - 1))
169 #define _VMALLOC_START _AC(0xfffffff500000000, UL) /* 4 GB */
170 #define HUGE_VMAP_BASE _AC(0xfffffff600000000, UL) /* 4 GB */
171 #define MEM_SV_START _AC(0xfffffff700000000, UL) /* 256 MB */
173 #define MEM_MODULE_START _AC(0xfffffff710000000, UL) /* 256 MB */
175 #define MEM_HV_START _AC(0xfffffff800000000, UL) /* 32 GB */
213 #define MEM_USER_INTRPT _AC(0xfc000000, UL)
215 #define MEM_SV_INTRPT _AC(0xfd000000, UL)
[all …]
/linux-3.4.99/arch/ia64/xen/
Dxencomm.c48 return 0UL; in xencomm_vtop()
67 return ~0UL; in xencomm_vtop()
71 return ~0UL; in xencomm_vtop()
75 return ~0UL; in xencomm_vtop()
79 return ~0UL; in xencomm_vtop()
97 return ~0UL; in xencomm_vtop()
102 return ~0UL; in xencomm_vtop()
/linux-3.4.99/arch/arm/mach-ep93xx/include/mach/
Dmemory.h9 #define PLAT_PHYS_OFFSET UL(0x00000000)
11 #define PLAT_PHYS_OFFSET UL(0xc0000000)
13 #define PLAT_PHYS_OFFSET UL(0xd0000000)
15 #define PLAT_PHYS_OFFSET UL(0xe0000000)
17 #define PLAT_PHYS_OFFSET UL(0xf0000000)
/linux-3.4.99/arch/m68k/mm/
Dinit_mm.c86 #define UL(x) ((unsigned long) (x)) in print_memmap() macro
87 #define MLK(b, t) UL(b), UL(t), (UL(t) - UL(b)) >> 10 in print_memmap()
88 #define MLM(b, t) UL(b), UL(t), (UL(t) - UL(b)) >> 20 in print_memmap()
/linux-3.4.99/arch/unicore32/include/mach/
Dmemory.h18 #define PHYS_OFFSET UL(0x00000000)
20 #define VECTORS_BASE UL(0xffff0000)
22 #define KUSER_BASE UL(0x80000000)
52 #define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000))

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