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Searched refs:REG_SET_BIT (Results 1 – 14 of 14) sorted by relevance

/linux-3.4.99/drivers/net/wireless/ath/ath9k/
Dmac.c140 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma()
141 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
142 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma()
416 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | in ath9k_hw_resettxqueue()
432 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); in ath9k_hw_resettxqueue()
435 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); in ath9k_hw_resettxqueue()
440 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); in ath9k_hw_resettxqueue()
446 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
451 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
474 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
[all …]
Dar9002_calib.c77 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
259 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
723 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
725 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
726 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
730 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
742 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
743 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
744 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
752 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
[all …]
Dcalib.c225 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
232 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
235 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
278 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
Dhw.c729 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
822 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
1001 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1126 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1194 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1694 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1728 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1786 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
1790 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1794 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
[all …]
Dar9002_hw.c401 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
455 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
457 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar9002_hw_enable_async_fifo()
460 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
Dar9003_mci.c450 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ar9003_mci_observation_set_up()
454 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO); in ar9003_mci_observation_set_up()
779 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); in ar9003_mci_mute_bt()
874 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_reset()
884 REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN); in ar9003_mci_reset()
1033 REG_SET_BIT(ah, AR_BTCOEX_CTRL, in ar9003_mci_2g5g_switch()
1040 REG_SET_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_2g5g_switch()
1042 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_2g5g_switch()
Dar5008_phy.c647 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
672 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
690 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
704 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar5008_hw_override_ini()
838 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
1091 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_old()
1255 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1551 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
Dbtcoex.c141 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_2wire()
159 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_3wire()
Dar9003_phy.c549 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
576 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
589 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_override_ini()
864 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1192 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
Dar9003_calib.c59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
304 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_iqcalibrate()
973 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal()
993 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal()
Dar9002_phy.c434 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, in ar9002_olc_init()
Dar9003_hw.c742 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9003_hw_configpcipowersave()
Dar9003_paprd.c811 REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY, in ar9003_paprd_create_curve()
Dhw.h108 #define REG_SET_BIT(_a, _r, _f) \ macro