/linux-3.4.99/drivers/net/wireless/ath/ath9k/ |
D | ar9002_calib.c | 727 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal() 729 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal() 737 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal() 738 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal() 739 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal() 741 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal() 753 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal() 754 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal() 828 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal() 852 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
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D | mac.c | 154 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma() 155 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma() 156 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma() 636 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort() 648 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort() 668 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ath9k_hw_startpcureceive() 912 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
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D | calib.c | 229 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal() 274 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf() 276 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
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D | ar9003_mci.c | 821 REG_CLR_BIT(ah, AR_BTCOEX_CTRL, in ar9003_mci_osla_setup() 913 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_reset() 1027 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_2g5g_switch() 1029 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_2g5g_switch() 1044 REG_CLR_BIT(ah, AR_BTCOEX_CTRL, in ar9003_mci_2g5g_switch()
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D | hw.c | 727 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc() 1200 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode() 1726 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset() 1911 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep() 1921 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); in ath9k_set_power_sleep() 1968 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep() 2025 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake() 2629 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter() 2915 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start() 2939 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop() [all …]
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D | ar9003_paprd.c | 282 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, in ar9003_get_desired_gain() 778 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, in ar9003_paprd_setup_gain_table() 804 REG_CLR_BIT(ah, AR_PHY_CHAN_INFO_MEMORY, in ar9003_paprd_create_curve() 820 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, in ar9003_paprd_create_curve()
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D | ar9002_hw.c | 326 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave() 458 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
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D | ar9002_phy.c | 233 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate() 237 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate()
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D | ar5008_phy.c | 1094 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_old() 1258 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new() 1531 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar5008_hw_set_radar_params() 1553 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
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D | ar9003_phy.c | 867 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control() 1172 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params() 1194 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
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D | btcoex.c | 137 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_2wire()
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D | ar9003_calib.c | 970 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal() 996 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal()
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D | hw.h | 110 #define REG_CLR_BIT(_a, _r, _f) \ macro
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