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Searched refs:PLL_BASE_DIVN_MASK (Results 1 – 2 of 2) sorted by relevance

/linux-3.4.99/arch/arm/mach-tegra/
Dtegra30_clocks.c152 #define PLL_BASE_DIVN_MASK (0x3FF<<8) macro
912 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; in tegra30_pll_clk_init()
1054 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || in tegra30_pll_clk_set_rate()
1068 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | in tegra30_pll_clk_set_rate()
Dtegra2_clocks.c88 #define PLL_BASE_DIVN_MASK (0x3FF<<8) macro
631 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; in tegra2_pll_clk_init()
682 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK | in tegra2_pll_clk_set_rate()