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Searched refs:PLLU_BASE_POST_DIV (Results 1 – 2 of 2) sorted by relevance

/linux-3.4.99/arch/arm/mach-tegra/
Dtegra30_clocks.c177 #define PLLU_BASE_POST_DIV (1<<20) macro
915 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; in tegra30_pll_clk_init()
1008 p_div = PLLU_BASE_POST_DIV; in tegra30_pll_clk_set_rate()
1069 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); in tegra30_pll_clk_set_rate()
Dtegra2_clocks.c109 #define PLLU_BASE_POST_DIV (1<<20) macro
634 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; in tegra2_pll_clk_init()
689 val |= PLLU_BASE_POST_DIV; in tegra2_pll_clk_set_rate()