Searched refs:PACKET3_SET_CONFIG_REG_START (Results 1 – 7 of 7) sorted by relevance
95 radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); in cp_set_surface_sync()256 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); in draw_auto()552 radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); in set_default_state()557 radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); in set_default_state()562 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); in set_default_state()
549 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
866 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
2280 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_packet3_check()2282 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in evergreen_packet3_check()2856 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_vm_packet3_check()2858 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in evergreen_vm_packet3_check()
1161 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in cayman_fence_ring_emit()1195 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in cayman_ring_ib_execute()
1910 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()1953 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_ring_ib_execute()2764 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()2766 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in si_vm_packet3_gfx_check()
761 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro