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/linux-3.4.99/arch/arm/kernel/
Dperf_event_v7.c136 [C(L1D)] = {
143 [C(OP_READ)] = {
144 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
145 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
147 [C(OP_WRITE)] = {
148 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
149 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
151 [C(OP_PREFETCH)] = {
152 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
153 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
[all …]
Dperf_event_v6.c82 [C(L1D)] = {
89 [C(OP_READ)] = {
90 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
91 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
93 [C(OP_WRITE)] = {
94 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
95 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
97 [C(OP_PREFETCH)] = {
98 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
99 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
[all …]
Dperf_event_xscale.c65 [C(L1D)] = {
66 [C(OP_READ)] = {
67 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
68 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
70 [C(OP_WRITE)] = {
71 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
72 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
74 [C(OP_PREFETCH)] = {
75 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
76 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
[all …]
/linux-3.4.99/arch/sh/kernel/cpu/sh4a/
Dperf_event.c112 #define C(x) PERF_COUNT_HW_CACHE_##x macro
119 [ C(L1D) ] = {
120 [ C(OP_READ) ] = {
121 [ C(RESULT_ACCESS) ] = 0x0031,
122 [ C(RESULT_MISS) ] = 0x0032,
124 [ C(OP_WRITE) ] = {
125 [ C(RESULT_ACCESS) ] = 0x0039,
126 [ C(RESULT_MISS) ] = 0x003a,
128 [ C(OP_PREFETCH) ] = {
129 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux-3.4.99/arch/sh/kernel/cpu/sh4/
Dperf_event.c87 #define C(x) PERF_COUNT_HW_CACHE_##x macro
94 [ C(L1D) ] = {
95 [ C(OP_READ) ] = {
96 [ C(RESULT_ACCESS) ] = 0x0001,
97 [ C(RESULT_MISS) ] = 0x0004,
99 [ C(OP_WRITE) ] = {
100 [ C(RESULT_ACCESS) ] = 0x0002,
101 [ C(RESULT_MISS) ] = 0x0005,
103 [ C(OP_PREFETCH) ] = {
104 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux-3.4.99/arch/x86/kernel/cpu/
Dperf_event_intel.c150 [ C(L1D) ] = {
151 [ C(OP_READ) ] = {
152 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
153 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
155 [ C(OP_WRITE) ] = {
156 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
157 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
159 [ C(OP_PREFETCH) ] = {
160 [ C(RESULT_ACCESS) ] = 0x0,
161 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
[all …]
Dperf_event_amd.c15 [ C(L1D) ] = {
16 [ C(OP_READ) ] = {
17 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
18 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
20 [ C(OP_WRITE) ] = {
21 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
22 [ C(RESULT_MISS) ] = 0,
24 [ C(OP_PREFETCH) ] = {
25 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
26 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
/linux-3.4.99/lib/
Dsha1.c54 #define SHA_ROUND(t, input, fn, constant, A, B, C, D, E) do { \ argument
59 #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
60 #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
61 #define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) argument
62 #define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D,… argument
63 #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) argument
83 __u32 A, B, C, D, E; in sha_transform() local
87 C = digest[2]; in sha_transform()
92 T_0_15( 0, A, B, C, D, E); in sha_transform()
93 T_0_15( 1, E, A, B, C, D); in sha_transform()
[all …]
/linux-3.4.99/arch/sparc/kernel/
Dperf_event.c131 #define C(x) PERF_COUNT_HW_CACHE_##x macro
167 [C(L1D)] = {
168 [C(OP_READ)] = {
169 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
170 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
172 [C(OP_WRITE)] = {
173 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
174 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
176 [C(OP_PREFETCH)] = {
177 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
/linux-3.4.99/arch/mips/kernel/
Dperf_event_mipsxx.c82 #define C(x) PERF_COUNT_HW_CACHE_##x macro
842 [C(L1D)] = {
849 [C(OP_READ)] = {
850 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
851 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
853 [C(OP_WRITE)] = {
854 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
855 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
857 [C(OP_PREFETCH)] = {
858 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
[all …]
/linux-3.4.99/arch/powerpc/perf/
De500-pmu.c29 #define C(x) PERF_COUNT_HW_CACHE_##x macro
36 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
41 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
42 [C(OP_READ)] = { 27, 0 },
43 [C(OP_WRITE)] = { 28, 0 },
44 [C(OP_PREFETCH)] = { 29, 0 },
46 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
47 [C(OP_READ)] = { 2, 60 },
48 [C(OP_WRITE)] = { -1, -1 },
49 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
Dmpc7450-pmu.c353 #define C(x) PERF_COUNT_HW_CACHE_##x macro
360 static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
361 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
362 [C(OP_READ)] = { 0, 0x225 },
363 [C(OP_WRITE)] = { 0, 0x227 },
364 [C(OP_PREFETCH)] = { 0, 0 },
366 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
367 [C(OP_READ)] = { 0x129, 0x115 },
368 [C(OP_WRITE)] = { -1, -1 },
369 [C(OP_PREFETCH)] = { 0x634, 0 },
[all …]
Dpower7-pmu.c309 #define C(x) PERF_COUNT_HW_CACHE_##x macro
316 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
317 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
318 [C(OP_READ)] = { 0xc880, 0x400f0 },
319 [C(OP_WRITE)] = { 0, 0x300f0 },
320 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
322 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
323 [C(OP_READ)] = { 0, 0x200fc },
324 [C(OP_WRITE)] = { -1, -1 },
325 [C(OP_PREFETCH)] = { 0x408a, 0 },
[all …]
Dpower6-pmu.c480 #define C(x) PERF_COUNT_HW_CACHE_##x macro
488 static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
489 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
490 [C(OP_READ)] = { 0x280030, 0x80080 },
491 [C(OP_WRITE)] = { 0x180032, 0x80088 },
492 [C(OP_PREFETCH)] = { 0x810a4, 0 },
494 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
495 [C(OP_READ)] = { 0, 0x100056 },
496 [C(OP_WRITE)] = { -1, -1 },
497 [C(OP_PREFETCH)] = { 0x4008c, 0 },
[all …]
Dppc970-pmu.c432 #define C(x) PERF_COUNT_HW_CACHE_##x macro
439 static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
440 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
441 [C(OP_READ)] = { 0x8810, 0x3810 },
442 [C(OP_WRITE)] = { 0x7810, 0x813 },
443 [C(OP_PREFETCH)] = { 0x731, 0 },
445 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
446 [C(OP_READ)] = { 0, 0 },
447 [C(OP_WRITE)] = { -1, -1 },
448 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
Dpower4-pmu.c552 #define C(x) PERF_COUNT_HW_CACHE_##x macro
559 static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
560 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
561 [C(OP_READ)] = { 0x8c10, 0x3c10 },
562 [C(OP_WRITE)] = { 0x7c10, 0xc13 },
563 [C(OP_PREFETCH)] = { 0xc35, 0 },
565 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
566 [C(OP_READ)] = { 0, 0 },
567 [C(OP_WRITE)] = { -1, -1 },
568 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
Dpower5-pmu.c560 #define C(x) PERF_COUNT_HW_CACHE_##x macro
567 static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
568 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
569 [C(OP_READ)] = { 0x4c1090, 0x3c1088 },
570 [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 },
571 [C(OP_PREFETCH)] = { 0xc70e7, 0 },
573 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
574 [C(OP_READ)] = { 0, 0 },
575 [C(OP_WRITE)] = { -1, -1 },
576 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
/linux-3.4.99/arch/blackfin/kernel/
Dperf_event.c81 #define C(x) PERF_COUNT_HW_CACHE_##x macro
87 [C(L1D)] = { /* Data bank A */
88 [C(OP_READ)] = {
89 [C(RESULT_ACCESS)] = 0,
90 [C(RESULT_MISS) ] = 0x9A,
92 [C(OP_WRITE)] = {
93 [C(RESULT_ACCESS)] = 0,
94 [C(RESULT_MISS) ] = 0,
96 [C(OP_PREFETCH)] = {
97 [C(RESULT_ACCESS)] = 0,
[all …]
/linux-3.4.99/scripts/rt-tester/
Dt5-l4-pi-boost-deboost-setsched.tst4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedfifo: 1: 81
56 C: schedfifo: 2: 82
57 C: schedfifo: 3: 83
58 C: schedfifo: 4: 84
61 C: locknowait: 0: 0
65 C: locknowait: 1: 1
[all …]
Dt5-l4-pi-boost-deboost.tst4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedfifo: 1: 81
56 C: schedfifo: 2: 82
57 C: schedfifo: 3: 83
58 C: schedfifo: 4: 84
61 C: locknowait: 0: 0
65 C: locknowait: 1: 1
[all …]
Dt4-l2-pi-deboost.tst4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedother: 1: 0
56 C: schedfifo: 2: 82
57 C: schedfifo: 3: 83
60 C: locknowait: 0: 0
64 C: locknowait: 1: 1
68 C: lockintnowait: 3: 0
[all …]
Dt2-l2-2rt-deadlock.tst4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedfifo: 0: 80
55 C: schedfifo: 1: 80
58 C: locknowait: 0: 0
62 C: locknowait: 1: 1
66 C: lockintnowait: 0: 1
70 C: lockintnowait: 1: 0
74 C: signal: 1: 0
[all …]
/linux-3.4.99/drivers/scsi/isci/
Dremote_device.h255 C(DEV_INITIAL),\
256 C(DEV_STOPPED),\
257 C(DEV_STARTING),\
258 C(DEV_READY),\
259 C(STP_DEV_IDLE),\
260 C(STP_DEV_CMD),\
261 C(STP_DEV_NCQ),\
262 C(STP_DEV_NCQ_ERROR),\
263 C(STP_DEV_ATAPI_ERROR),\
264 C(STP_DEV_AWAIT_RESET),\
[all …]
Drequest.h254 C(REQ_INIT),\
255 C(REQ_CONSTRUCTED),\
256 C(REQ_STARTED),\
257 C(REQ_STP_UDMA_WAIT_TC_COMP),\
258 C(REQ_STP_UDMA_WAIT_D2H),\
259 C(REQ_STP_NON_DATA_WAIT_H2D),\
260 C(REQ_STP_NON_DATA_WAIT_D2H),\
261 C(REQ_STP_PIO_WAIT_H2D),\
262 C(REQ_STP_PIO_WAIT_FRAME),\
263 C(REQ_STP_PIO_DATA_IN),\
[all …]
Dphy.h384 C(PHY_INITIAL),\
385 C(PHY_STOPPED),\
386 C(PHY_STARTING),\
387 C(PHY_SUB_INITIAL),\
388 C(PHY_SUB_AWAIT_OSSP_EN),\
389 C(PHY_SUB_AWAIT_SAS_SPEED_EN),\
390 C(PHY_SUB_AWAIT_IAF_UF),\
391 C(PHY_SUB_AWAIT_SAS_POWER),\
392 C(PHY_SUB_AWAIT_SATA_POWER),\
393 C(PHY_SUB_AWAIT_SATA_PHY_EN),\
[all …]

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