Lines Matching refs:C
136 [C(L1D)] = {
143 [C(OP_READ)] = {
144 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
145 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
147 [C(OP_WRITE)] = {
148 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
149 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
151 [C(OP_PREFETCH)] = {
152 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
153 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
156 [C(L1I)] = {
157 [C(OP_READ)] = {
158 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
159 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
161 [C(OP_WRITE)] = {
162 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
163 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
165 [C(OP_PREFETCH)] = {
166 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
167 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
170 [C(LL)] = {
171 [C(OP_READ)] = {
172 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
173 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
175 [C(OP_WRITE)] = {
176 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
177 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
179 [C(OP_PREFETCH)] = {
180 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
181 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
184 [C(DTLB)] = {
185 [C(OP_READ)] = {
186 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
187 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
189 [C(OP_WRITE)] = {
190 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
191 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
193 [C(OP_PREFETCH)] = {
194 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
195 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
198 [C(ITLB)] = {
199 [C(OP_READ)] = {
200 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
201 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
203 [C(OP_WRITE)] = {
204 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
205 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
207 [C(OP_PREFETCH)] = {
208 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
209 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
212 [C(BPU)] = {
213 [C(OP_READ)] = {
214 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
215 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
217 [C(OP_WRITE)] = {
218 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
219 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
221 [C(OP_PREFETCH)] = {
222 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
223 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
226 [C(NODE)] = {
227 [C(OP_READ)] = {
228 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
229 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
231 [C(OP_WRITE)] = {
232 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
233 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
235 [C(OP_PREFETCH)] = {
236 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
237 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
260 [C(L1D)] = {
267 [C(OP_READ)] = {
268 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
269 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
271 [C(OP_WRITE)] = {
272 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
273 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
275 [C(OP_PREFETCH)] = {
276 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
277 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
280 [C(L1I)] = {
281 [C(OP_READ)] = {
282 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
283 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
285 [C(OP_WRITE)] = {
286 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
287 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
289 [C(OP_PREFETCH)] = {
290 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
291 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
294 [C(LL)] = {
295 [C(OP_READ)] = {
296 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
297 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
299 [C(OP_WRITE)] = {
300 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
301 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
303 [C(OP_PREFETCH)] = {
304 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
305 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
308 [C(DTLB)] = {
309 [C(OP_READ)] = {
310 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
311 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
313 [C(OP_WRITE)] = {
314 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
315 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
317 [C(OP_PREFETCH)] = {
318 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
319 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
322 [C(ITLB)] = {
323 [C(OP_READ)] = {
324 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
325 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
327 [C(OP_WRITE)] = {
328 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
329 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
331 [C(OP_PREFETCH)] = {
332 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
333 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
336 [C(BPU)] = {
337 [C(OP_READ)] = {
338 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
339 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
341 [C(OP_WRITE)] = {
342 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
343 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
345 [C(OP_PREFETCH)] = {
346 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
347 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
350 [C(NODE)] = {
351 [C(OP_READ)] = {
352 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
353 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
355 [C(OP_WRITE)] = {
356 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
357 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
359 [C(OP_PREFETCH)] = {
360 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
361 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
384 [C(L1D)] = {
385 [C(OP_READ)] = {
386 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
387 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
389 [C(OP_WRITE)] = {
390 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
391 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
393 [C(OP_PREFETCH)] = {
394 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
395 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
398 [C(L1I)] = {
399 [C(OP_READ)] = {
400 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
401 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
403 [C(OP_WRITE)] = {
404 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
405 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
411 [C(OP_PREFETCH)] = {
412 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
413 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
416 [C(LL)] = {
417 [C(OP_READ)] = {
418 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
419 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
421 [C(OP_WRITE)] = {
422 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
423 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
425 [C(OP_PREFETCH)] = {
426 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
427 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
430 [C(DTLB)] = {
431 [C(OP_READ)] = {
432 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
433 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
435 [C(OP_WRITE)] = {
436 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
437 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
439 [C(OP_PREFETCH)] = {
440 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
441 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
444 [C(ITLB)] = {
445 [C(OP_READ)] = {
446 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
447 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
449 [C(OP_WRITE)] = {
450 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
451 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
453 [C(OP_PREFETCH)] = {
454 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
455 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
458 [C(BPU)] = {
459 [C(OP_READ)] = {
460 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
461 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
463 [C(OP_WRITE)] = {
464 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
465 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
467 [C(OP_PREFETCH)] = {
468 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
469 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
472 [C(NODE)] = {
473 [C(OP_READ)] = {
474 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
475 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
477 [C(OP_WRITE)] = {
478 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
479 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
481 [C(OP_PREFETCH)] = {
482 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
483 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
506 [C(L1D)] = {
507 [C(OP_READ)] = {
508 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
509 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
511 [C(OP_WRITE)] = {
512 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
513 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
515 [C(OP_PREFETCH)] = {
516 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
517 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
520 [C(L1I)] = {
527 [C(OP_READ)] = {
528 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
529 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
531 [C(OP_WRITE)] = {
532 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
533 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
535 [C(OP_PREFETCH)] = {
536 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
537 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
540 [C(LL)] = {
541 [C(OP_READ)] = {
542 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
543 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
545 [C(OP_WRITE)] = {
546 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
547 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
549 [C(OP_PREFETCH)] = {
550 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
551 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
554 [C(DTLB)] = {
555 [C(OP_READ)] = {
556 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
557 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
559 [C(OP_WRITE)] = {
560 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
561 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
563 [C(OP_PREFETCH)] = {
564 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
565 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
568 [C(ITLB)] = {
569 [C(OP_READ)] = {
570 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
571 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
573 [C(OP_WRITE)] = {
574 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
575 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
577 [C(OP_PREFETCH)] = {
578 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
579 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
582 [C(BPU)] = {
583 [C(OP_READ)] = {
584 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
585 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
587 [C(OP_WRITE)] = {
588 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
589 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
591 [C(OP_PREFETCH)] = {
592 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
593 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
596 [C(NODE)] = {
597 [C(OP_READ)] = {
598 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
599 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
601 [C(OP_WRITE)] = {
602 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
603 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
605 [C(OP_PREFETCH)] = {
606 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
607 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
630 [C(L1D)] = {
637 [C(OP_READ)] = {
638 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
639 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
641 [C(OP_WRITE)] = {
642 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
643 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
645 [C(OP_PREFETCH)] = {
646 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
647 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
650 [C(L1I)] = {
651 [C(OP_READ)] = {
652 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
653 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
655 [C(OP_WRITE)] = {
656 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
657 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
659 [C(OP_PREFETCH)] = {
660 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
661 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
664 [C(LL)] = {
665 [C(OP_READ)] = {
666 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
667 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
669 [C(OP_WRITE)] = {
670 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
671 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
673 [C(OP_PREFETCH)] = {
674 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
675 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
678 [C(DTLB)] = {
679 [C(OP_READ)] = {
680 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
681 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
683 [C(OP_WRITE)] = {
684 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
685 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
687 [C(OP_PREFETCH)] = {
688 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
689 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
692 [C(ITLB)] = {
693 [C(OP_READ)] = {
694 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
695 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
697 [C(OP_WRITE)] = {
698 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
699 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
701 [C(OP_PREFETCH)] = {
702 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
703 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
706 [C(BPU)] = {
707 [C(OP_READ)] = {
708 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
709 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
711 [C(OP_WRITE)] = {
712 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
713 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
715 [C(OP_PREFETCH)] = {
716 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
717 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
720 [C(NODE)] = {
721 [C(OP_READ)] = {
722 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
723 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
725 [C(OP_WRITE)] = {
726 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
727 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
729 [C(OP_PREFETCH)] = {
730 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
731 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,