| /linux-3.4.99/drivers/scsi/ |
| D | tmscsim.h | 185 #define BIT6 0x00000040 macro
212 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
240 #define DATAIN BIT6
390 #define ILLEGAL_OP_ERR BIT6
399 #define INVALID_CMD BIT6
423 #define DIS_INT_ON_SCSI_RST BIT6
428 #define EN_FEATURE BIT6
433 #define EN_QTAG_MSG BIT6
441 #define EATER_35NS BIT6
442 #define EATER_0NS (BIT7+BIT6)
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| D | dc395x.h | 69 #define BIT6 0x00000040 macro
137 #define DATAIN BIT6
179 #define EN_ATN_STOP BIT6
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| /linux-3.4.99/drivers/staging/vt6655/ |
| D | 80211hdr.h | 44 #define BIT6 0x00000040 macro
166 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
188 #define WLAN_GET_CAP_INFO_PBCC(n) ((((n) >> 8) & BIT6) >> 6)
201 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
224 #define WLAN_GET_CAP_INFO_PBCC(n) (((n) & BIT6) >> 6)
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| D | hostap.h | 42 #define WLAN_RATE_12M BIT6
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| /linux-3.4.99/drivers/staging/vt6656/ |
| D | 80211hdr.h | 42 #define BIT6 0x00000040 macro
163 & (BIT4|BIT5|BIT6|BIT7)) >> 4)
185 #define WLAN_GET_CAP_INFO_PBCC(n) ((((n) >> 8) & BIT6) >> 6)
197 #define WLAN_GET_FC_FSTYPE(n) ((((WORD)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
218 #define WLAN_GET_CAP_INFO_PBCC(n) (((n) & BIT6) >> 6)
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| D | hostap.h | 42 #define WLAN_RATE_12M BIT6
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| /linux-3.4.99/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 236 #define IMR_MGNTDOK BIT6
251 #define TPPoll_MQ BIT6
291 #define AcmHw_VoqStatus BIT6
381 #define RRSR_12M BIT6
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| /linux-3.4.99/drivers/video/via/ |
| D | lcd.c | 390 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
625 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
634 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
647 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
677 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
686 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
702 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
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| D | dvi.c | 69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
76 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
435 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
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| D | hw.c | 1684 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1691 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1695 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2048 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2050 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2056 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2058 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
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| D | share.h | 34 #define BIT6 0x40 macro
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| /linux-3.4.99/drivers/staging/keucr/ |
| D | smilecc.c | 42 #define BIT6 0x40 macro
110 if ((a&BIT6) != 0) { /* If D_all(all bit XOR) = 1 */ in calculate_ecc()
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| /linux-3.4.99/drivers/staging/rtl8192u/ |
| D | r8192U_hw.h | 235 #define AcmHw_VoqStatus BIT6
313 #define RRSR_12M BIT6
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| /linux-3.4.99/drivers/char/pcmcia/ |
| D | synclink_cs.c | 300 #define IRQ_EXITHUNT BIT6 // receive frame start
301 #define IRQ_RXTIME BIT6 // rx char timeout
308 #define XFW BIT6 // transmit FIFO write enable
671 #define CMD_RXRESET BIT6 // receiver reset
920 if (status & (BIT7 + BIT6)) { in rx_ready_async()
934 else if (status & BIT6) in rx_ready_async()
1478 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1480 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2186 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2188 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
[all …]
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| /linux-3.4.99/drivers/net/hamradio/ |
| D | z8530.h | 117 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-3.4.99/drivers/tty/serial/ |
| D | zs.h | 172 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | ip22zilog.h | 153 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | sunzilog.h | 155 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | pmac_zilog.h | 246 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-3.4.99/drivers/tty/ |
| D | synclinkmp.c | 417 #define RXINTE BIT6
423 #define IDLE BIT6
436 #define PMP BIT6
437 #define SHRT BIT6
2608 if (timerstatus0 & (BIT7 | BIT6)) in synclinkmp_interrupt()
2612 if (timerstatus1 & (BIT7 | BIT6)) in synclinkmp_interrupt()
4439 RegValue=BIT6; in async_mode()
4448 RegValue=BIT6; in async_mode()
4576 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ in hdlc_mode()
4604 RegValue |= BIT6; in hdlc_mode()
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| D | synclink_gt.c | 422 #define IRQ_CTS BIT6
1425 value |= BIT6; in set_break()
1427 value &= ~BIT6; in set_break()
4012 wr_reg32(info, RDCSR, BIT6); in rx_start()
4025 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4322 val |= BIT6; in sync_mode()
4414 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
4416 val |= BIT6; /* 010, txclk = BRG */ in sync_mode()
4445 val = BIT7 + BIT6; break; in sync_mode()
4446 default: val = BIT6; // NRZ encodings in sync_mode()
[all …]
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| /linux-3.4.99/include/linux/ |
| D | synclink.h | 24 #define BIT6 0x0040 macro
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| /linux-3.4.99/drivers/net/wan/ |
| D | z85230.h | 138 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-3.4.99/drivers/staging/rtl8187se/ |
| D | r8180_rtl8225z2.c | 903 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6)))); in SetZebraRFPowerState8185()
964 (u1bTmp | BIT5 | BIT6)); in SetZebraRFPowerState8185()
1024 write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); in SetZebraRFPowerState8185()
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| D | r8180_hw.h | 30 #define BIT6 0x00000040 macro
|