Lines Matching refs:BIT6
300 #define IRQ_EXITHUNT BIT6 // receive frame start
301 #define IRQ_RXTIME BIT6 // rx char timeout
308 #define XFW BIT6 // transmit FIFO write enable
671 #define CMD_RXRESET BIT6 // receiver reset
920 if (status & (BIT7 + BIT6)) { in rx_ready_async()
934 else if (status & BIT6) in rx_ready_async()
1478 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1480 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2186 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2188 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
3165 val |= BIT6; in hdlc_mode()
3168 val |= BIT6; in hdlc_mode()
3171 val |= BIT7 + BIT6; in hdlc_mode()
3255 clear_reg_bits(info, CHA + CCR0, BIT6); in hdlc_mode()
3422 val |= BIT6; in async_mode()
3605 val &= ~BIT6; in set_signals()
3607 val |= BIT6; in set_signals()
3664 else if (status & BIT6) in rx_get_frame()