Searched refs:mtr (Results 1 – 8 of 8) sorted by relevance
283 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) argument284 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) argument285 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) argument286 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument287 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) argument288 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) argument289 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) argument290 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument291 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument292 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument[all …]
107 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ member174 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) argument175 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) argument176 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument177 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) argument178 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) argument179 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument181 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument182 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument183 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) argument[all …]
278 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8)) argument279 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4) argument280 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4) argument281 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) argument282 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1) argument283 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) argument284 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument285 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument286 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument287 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) argument[all …]
330 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; member655 if (!priv->mtr[chan][chan_rank].present) in i5100_npages()660 priv->mtr[chan][chan_rank].numcol + in i5100_npages()661 priv->mtr[chan][chan_rank].numrow + in i5100_npages()662 priv->mtr[chan][chan_rank].numbank; in i5100_npages()686 priv->mtr[i][j].present = i5100_mtr_present(w); in i5100_init_mtr()687 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); in i5100_init_mtr()688 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); in i5100_init_mtr()689 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); in i5100_init_mtr()690 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); in i5100_init_mtr()[all …]
35 tsunami_64 mtr; member
36 titan_64 mtr; member
393 printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); in tsunami_init_arch()
371 printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr); in titan_init_arch()