107 	u16 mtr[MAX_SLOTS][MAX_BRANCHES];	/* Memory Technlogy Reg */  member
174 #define MTR_DIMMS_PRESENT(mtr)		((mtr) & (1 << 8))  argument
175 #define MTR_DIMMS_ETHROTTLE(mtr)	((mtr) & (1 << 7))  argument
176 #define MTR_DRAM_WIDTH(mtr)		(((mtr) & (1 << 6)) ? 8 : 4)  argument
177 #define MTR_DRAM_BANKS(mtr)		(((mtr) & (1 << 5)) ? 8 : 4)  argument
178 #define MTR_DIMM_RANKS(mtr)		(((mtr) & (1 << 4)) ? 1 : 0)  argument
179 #define MTR_DIMM_ROWS(mtr)		(((mtr) >> 2) & 0x3)  argument
181 #define MTR_DIMM_ROWS_ADDR_BITS(mtr)	(MTR_DIMM_ROWS(mtr) + 13)  argument
182 #define MTR_DIMM_COLS(mtr)		((mtr) & 0x3)  argument
183 #define MTR_DIMM_COLS_ADDR_BITS(mtr)	(MTR_DIMM_COLS(mtr) + 10)  argument
622 	int mtr, ans, addrBits, channel;  in decode_mtr()  local
626 	mtr = pvt->mtr[slot][branch];  in decode_mtr()
627 	ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;  in decode_mtr()
641 	addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);  in decode_mtr()
643 	addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);  in decode_mtr()
645 	addrBits += MTR_DIMM_RANKS(mtr);  in decode_mtr()
654 	debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));  in decode_mtr()
657 		MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");  in decode_mtr()
659 	debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));  in decode_mtr()
660 	debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");  in decode_mtr()
661 	debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);  in decode_mtr()
662 	debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);  in decode_mtr()
684 		if (MTR_DRAM_WIDTH(mtr) == 8)  in decode_mtr()
691 	if (MTR_DRAM_WIDTH(mtr) == 8) {  in decode_mtr()
700 	return mtr;  in decode_mtr()
778 	int mtr;  in i7300_init_csrows()  local
810 					&pvt->mtr[slot][branch]);  in i7300_init_csrows()
817 				mtr = decode_mtr(pvt, slot, ch, branch,  in i7300_init_csrows()
820 				if (!MTR_DIMMS_PRESENT(mtr))  in i7300_init_csrows()