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Searched refs:__SYSREG (Results 1 – 24 of 24) sorted by relevance

/linux-2.6.39/arch/mn10300/include/asm/
Dtimer-regs.h23 #define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
30 #define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
44 #define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */
58 #define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */
72 #define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */
87 #define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
89 #define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */
90 #define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */
91 #define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */
92 #define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */
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Dcpu-regs.h30 #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) macro
33 #define __SYSREG(ADDR, TYPE) ADDR
88 #define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
95 #define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
122 #define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
125 #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
126 #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
127 #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
128 #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
129 #define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
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Drtc-regs.h18 #define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
19 #define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
20 #define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
21 #define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
22 #define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */
23 #define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
24 #define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
25 #define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */
26 #define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */
27 #define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */
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Dpio-regs.h20 #define P0MD __SYSREG(0xdb000000, u16) /* mode reg */
57 #define P0IN __SYSREG(0xdb000004, u8) /* in reg */
58 #define P0OUT __SYSREG(0xdb000008, u8) /* out reg */
60 #define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */
79 #define P1MD __SYSREG(0xdb000100, u16) /* mode reg */
106 #define P1IN __SYSREG(0xdb000104, u8) /* in reg */
107 #define P1OUT __SYSREG(0xdb000108, u8) /* out reg */
108 #define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */
121 #define P2MD __SYSREG(0xdb000200, u16) /* mode reg */
142 #define P2IN __SYSREG(0xdb000204, u8) /* in reg */
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Dserial-regs.h21 #define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
68 #define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
75 #define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
76 #define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
78 #define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
96 #define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
97 #define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
98 #define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
99 #define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
100 #define SC1STR __SYSREG(0xd400201c, u16) /* status reg */
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Dcache.h32 __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
36 __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
38 __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
40 __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
42 __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
46 __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \
49 __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \
54 __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \
57 __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \
Dbusctl-regs.h20 #define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */
50 #define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */
76 #define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */
81 #define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */
89 #define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */
97 #define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */
119 #define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */
125 #define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */
144 #define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */
147 #define SDSHDW __SYSREG(0xda000010, u32) /* test reg */
Dreset-regs.h29 #define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */
39 #define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
Dintctl-regs.h23 __SYSREG(0xd4000000 + (X) * 4 + \
27 __SYSREG(0xd4000000 + (X) * 4 + \
/linux-2.6.39/arch/mn10300/proc-mn2ws0050/include/proc/
Dnand-regs.h20 #define FCOMMAND_0 __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */
21 #define FCOMMAND_1 __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */
22 #define FCOMMAND_2 __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */
23 #define FCOMMAND_3 __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */
26 #define FCOMMAND2_0 __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */
27 #define FCOMMAND2_1 __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */
28 #define FCOMMAND2_2 __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */
29 #define FCOMMAND2_3 __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */
59 #define FADD __SYSREG(0xd8f00004, u32)
61 #define FADD2 __SYSREG(0xd8f00008, u32)
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Dsmp-regs.h31 #define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
33 #define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
41 #define ECHCTR __SYSREG(0xc0000c20, u32)
47 #define NMIAGR __SYSREG(0xd400013c, u16)
Ddmactl-regs.h19 #define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */
69 #define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */
71 #define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */
73 #define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */
76 #define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */
Dintctl-regs.h9 #define IAGR __SYSREG(0xd4000100, u16)
25 #define EXTMD0 __SYSREG(0xd4000200, u32)
/linux-2.6.39/arch/mn10300/unit-asb2364/include/unit/
Dfpga-regs.h11 #define ASB2364_FPGA_REG_RESET_LAN __SYSREG(0xa9001300, u16)
12 #define ASB2364_FPGA_REG_RESET_UART __SYSREG(0xa9001304, u16)
13 #define ASB2364_FPGA_REG_RESET_I2C __SYSREG(0xa9001308, u16)
14 #define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16)
15 #define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16)
17 #define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16)
24 #define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16)
31 #define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16)
32 #define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16)
33 #define ASB2364_FPGA_REG_CPLD6_SET1 __SYSREG(0xa9002600, u16)
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Dserial.h62 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 2, u8)
63 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 2, u8)
64 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 2, u8)
65 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 2, u8)
66 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)
67 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 2, u8)
68 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8)
69 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8)
70 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 2, u8)
71 #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 2, u8)
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Dsmsc911x.h44 #define IIC_DTRM __SYSREG(0xd8400000 + IIC_OFFSET, u32)
45 #define IIC_DREC __SYSREG(0xd8400004 + IIC_OFFSET, u32)
46 #define IIC_MYADD __SYSREG(0xd8400008 + IIC_OFFSET, u32)
47 #define IIC_CLK __SYSREG(0xd840000c + IIC_OFFSET, u32)
48 #define IIC_BRST __SYSREG(0xd8400010 + IIC_OFFSET, u32)
49 #define IIC_HOLD __SYSREG(0xd8400014 + IIC_OFFSET, u32)
50 #define IIC_BSTS __SYSREG(0xd8400018 + IIC_OFFSET, u32)
51 #define IIC_ICR __SYSREG(0xd4000080 + 4 * USE_IIC_CH, u16)
Dleds.h21 #define ASB2364_7SEGLEDS __SYSREG(0xA9001630, u32)
/linux-2.6.39/arch/mn10300/unit-asb2303/include/unit/
Dserial.h65 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
66 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
67 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
68 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
69 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
70 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
71 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
72 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
73 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
74 #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
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Dleds.h19 #define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32)
20 #define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32)
/linux-2.6.39/arch/mn10300/unit-asb2305/include/unit/
Dserial.h19 #define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8)
56 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
57 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
58 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
59 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
60 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
61 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
62 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
63 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
64 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
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Dleds.h19 #define ASB2305_7SEGLEDS __SYSREG(0xA6F90000, u32)
/linux-2.6.39/arch/mn10300/proc-mn103e010/include/proc/
Ddmactl-regs.h20 #define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
67 #define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
69 #define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
71 #define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
74 #define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
Dintctl-regs.h9 #define IAGR __SYSREG(0xd4000100, u16)
25 #define EXTMD __SYSREG(0xd4000200, u16)
/linux-2.6.39/arch/mn10300/unit-asb2364/
Dunit-init.c28 #define TTYS0_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)
29 #define LAN_IRQ_CFG __SYSREG(SMSC911X_BASE + 0x54, u32)
30 #define LAN_INT_EN __SYSREG(SMSC911X_BASE + 0x5c, u32)
128 #define IRQCTL __SYSREG(0xd5000090, u32) in unit_init_IRQ()