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Searched refs:TSUNAMI_cchip (Results 1 – 3 of 3) sorted by relevance

/linux-2.6.39/arch/alpha/kernel/
Dcore_tsunami.c225 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
229 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
230 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
231 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
383 tmp = (unsigned long)(TSUNAMI_cchip - 1); in tsunami_init_arch()
392 printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr); in tsunami_init_arch()
393 printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); in tsunami_init_arch()
394 printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr); in tsunami_init_arch()
395 printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr); in tsunami_init_arch()
396 printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr); in tsunami_init_arch()
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Dsys_dp264.c50 register tsunami_cchip *cchip = TSUNAMI_cchip; in tsunami_update_irq_hw()
201 pld = TSUNAMI_cchip->dir0.csr; in dp264_device_interrupt()
215 TSUNAMI_cchip->dir0.csr = 1UL << i; mb(); in dp264_device_interrupt()
216 tmp = TSUNAMI_cchip->dir0.csr; in dp264_device_interrupt()
/linux-2.6.39/arch/alpha/include/asm/
Dcore_tsunami.h88 #define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL)) macro