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Searched refs:SW (Results 1 – 25 of 30) sorted by relevance

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/linux-2.6.39/arch/ia64/kernel/
Dentry.h24 #define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET) macro
42 .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
43 .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
44 .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \
45 .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \
46 .spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off); \
47 .spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off); \
48 .spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off); \
49 .spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off); \
50 .spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off); \
[all …]
Dentry.S257 adds r14=SW(R4)+16,sp
267 adds r15=SW(R5)+16,sp
271 add r14=SW(R4)+16,sp
273 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
281 adds r15=SW(R5)+16,sp
284 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
286 add r2=SW(F2)+16,sp // r2 = &sw->f2
288 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
290 add r3=SW(F3)+16,sp // r3 = &sw->f3
297 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
[all …]
Dmca_asm.S566 add temp1=SW(F2), regs
567 add temp2=SW(F3), regs
602 stf.spill [temp1]=f30,SW(B2)-SW(F30)
603 stf.spill [temp2]=f31,SW(B3)-SW(F31)
612 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
725 add temp1=SW(F2), regs
726 add temp2=SW(F3), regs
761 ldf.fill f30=[temp1],SW(B2)-SW(F30)
762 ldf.fill f31=[temp2],SW(B3)-SW(F31)
769 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
Dunwind.c2253 unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(CALLER_UNAT); in unw_init()
2254 unw.sw_off[unw.preg_index[UNW_REG_BSPSTORE]] = SW(AR_BSPSTORE); in unw_init()
2255 unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_PFS); in unw_init()
2256 unw.sw_off[unw.preg_index[UNW_REG_RP]] = SW(B0); in unw_init()
2257 unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(CALLER_UNAT); in unw_init()
2258 unw.sw_off[unw.preg_index[UNW_REG_PR]] = SW(PR); in unw_init()
2259 unw.sw_off[unw.preg_index[UNW_REG_LC]] = SW(AR_LC); in unw_init()
2260 unw.sw_off[unw.preg_index[UNW_REG_FPSR]] = SW(AR_FPSR); in unw_init()
2261 for (i = UNW_REG_R4, off = SW(R4); i <= UNW_REG_R7; ++i, off += 8) in unw_init()
2263 for (i = UNW_REG_B1, off = SW(B1); i <= UNW_REG_B5; ++i, off += 8) in unw_init()
[all …]
/linux-2.6.39/arch/powerpc/kernel/
Dalign.c46 #define SW 0x20 /* byte swap */ macro
138 { 4, LD+SW }, /* 10 0 1000: lwbrx */
140 { 4, ST+SW }, /* 10 0 1010: stwbrx */
142 { 2, LD+SW }, /* 10 0 1100: lhbrx */
144 { 2, ST+SW }, /* 10 0 1110: sthbrx */
298 if (swiz == 0 && (flags & SW)) in emulate_multiple()
318 bswiz = (flags & SW)? 3: 0; in emulate_multiple()
379 if (flags & SW) in emulate_fp_pair()
581 if (flags & SW) { in emulate_spe()
663 if (flags & SW) in emulate_vsx()
[all …]
/linux-2.6.39/arch/parisc/include/asm/
Dfloppy.h41 #define SW fd_routine[use_virtual_dma&1] macro
53 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
54 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
55 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/linux-2.6.39/Documentation/misc-devices/
Deeprom30 Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37
31 Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37
32 Catalyst 34RC02 2K 0x50 - 0x57, SW write protect at 0x30-37
33 Fairchild 34W02 2K 0x50 - 0x57, SW write protect at 0x30-37
34 Microchip 24AA52 2K 0x50 - 0x57, SW write protect at 0x30-37
35 ST M34C02 2K 0x50 - 0x57, SW write protect at 0x30-37
/linux-2.6.39/arch/x86/include/asm/
Dfloppy.h30 #define SW fd_routine[use_virtual_dma & 1] macro
42 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
43 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
44 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/linux-2.6.39/Documentation/networking/
DREADME.ipw2100164 1 = SW based RF kill active (radio off)
166 3 = Both HW and SW RF kill active (radio off)
168 0 = If SW based RF kill active, turn the radio back on
169 1 = If radio is on, activate SW based RF kill
171 NOTE: If you enable the SW based RF kill and then toggle the HW
DREADME.ipw2200294 1 = SW based RF kill active (radio off)
296 3 = Both HW and SW RF kill active (radio off)
298 0 = If SW based RF kill active, turn the radio back on
299 1 = If radio is on, activate SW based RF kill
301 NOTE: If you enable the SW based RF kill and then toggle the HW
Dpktgen.txt17 root 129 0.3 0.0 0 0 ? SW 2003 523:20 [pktgen/0]
18 root 130 0.3 0.0 0 0 ? SW 2003 509:50 [pktgen/1]
Dstmmac.txt127 flag the csum will be done in SW on JUMBO frames.
Darcnet-hardware.txt1017 | U3 SW 1 JP0 ###| Phone Jacks
1691 SW 1 : Shared Memory Address and I/O Base
1724 SW 2 : Node ID (binary coded)
2192 | SW 3 SW 1 | |
2597 > | SW? || SW? | |
2797 Although the jumpers SW1 and SW3 are marked SW, not JP, they are jumpers, not
/linux-2.6.39/drivers/regulator/
Dmc13xxx.h97 MC13xxx_DEFINE(SW, _name, _reg, _vsel_reg, _voltages, ops)
/linux-2.6.39/drivers/gpu/drm/nouveau/
Dnv20_graph.c786 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */ in nv20_graph_register()
809 NVOBJ_CLASS(dev, 0x506e, SW); in nv20_graph_register()
824 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */ in nv30_graph_register()
853 NVOBJ_CLASS(dev, 0x506e, SW); in nv30_graph_register()
Dnv40_graph.c444 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */ in nv40_graph_register()
468 NVOBJ_CLASS(dev, 0x506e, SW); in nv40_graph_register()
Dnv10_graph.c1072 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */ in nv10_graph_register()
1107 NVOBJ_CLASS(dev, 0x506e, SW); in nv10_graph_register()
Dnvc0_fifo.c299 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */ in nvc0_fifo_create()
Dnv04_graph.c1222 NVOBJ_CLASS(dev, 0x506e, SW); in nv04_graph_register()
Dnv50_graph.c453 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */ in nv50_graph_register()
/linux-2.6.39/drivers/message/i2o/
DREADME.ioctl220 Please note that SW transfers can take a long time.
262 Please note that SW transfers can take a long time.
/linux-2.6.39/Documentation/i2o/
Dioctl220 Please note that SW transfers can take a long time.
262 Please note that SW transfers can take a long time.
/linux-2.6.39/arch/arm/mm/
Dproc-v7.S383 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
/linux-2.6.39/drivers/input/
Dinput.c1386 INPUT_DEV_CAP_ATTR(SW, sw);
1801 INPUT_CLEANSE_BITMASK(dev, SW, sw); in input_cleanse_bitmasks()
/linux-2.6.39/drivers/mfd/
DKconfig189 driver supports both RT and SW conversion methods.

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