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Searched refs:PLL (Results 1 – 25 of 32) sorted by relevance

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/linux-2.6.39/Documentation/dvb/
Dcards.txt14 tuner/PLL chips, and not all combinations are supported. Often
15 the demodulator and tuner/PLL chip are inside a metal box for
23 - cx24110 : Conexant HM1221/HM1811 (cx24110 or cx24106 demod, cx24108 PLL)
24 - grundig_29504-491 : Grundig 29504-491 (Philips TDA8083 demodulator), tsa5522 PLL
26 - stv0299 : Alps BSRU6 (tsa5059 PLL), LG TDQB-S00x (tsa5059 PLL),
27 LG TDQF-S001F (sl1935 PLL), Philips SU1278 (tua6100 PLL),
28 Philips SU1278SH (tsa5059 PLL), Samsung TBMU24112IMB, Technisat Sky2Pc with bios Rev. 2.6
30 - ves1820 : various (ves1820 demodulator, sp5659c or spXXXX PLL)
31 - at76c651 : Atmel AT76c651(B) with DAT7021 PLL
33 - alps_tdlb7 : Alps TDLB7 (sp8870 demodulator, sp5659 PLL)
[all …]
Dtechnisat.txt42 b.) => "Generic I2C PLL based tuners"
46 b.) => "Generic I2C PLL based tuners"
60 b.) => "Generic I2C PLL based tuners"
64 b.) => "Generic I2C PLL based tuners"
71 b.) => "Generic I2C PLL based tuners"
/linux-2.6.39/Documentation/arm/Samsung-S3C24XX/
DCPUfreq.txt15 PLL to feed the ARM, memory and peripherals via a series of dividers
17 newer version where there is a separate PLL and clock divider for the
26 system. Each CPU registers a driver to control the PLL, clock dividers
38 SoC and the driver as each device has different PLL and clock chains
45 The SLOW mode where the PLL is turned off altogether and the
/linux-2.6.39/arch/unicore32/kernel/
Dsleep.S103 @ prepare PMCR for PLL changing
106 @ prepare for closing PLL
122 @ change PLL
129 @ wait for PLL changing complete
138 @ close PLL
/linux-2.6.39/drivers/media/dvb/b2c2/
Dflexcop-fe-tuner.c69 #if FE_SUPPORTED(MT312) && FE_SUPPORTED(PLL)
185 #if FE_SUPPORTED(STV0299) && FE_SUPPORTED(PLL)
409 #if FE_SUPPORTED(MT352) && FE_SUPPORTED(PLL)
471 #if FE_SUPPORTED(NXT200X) && FE_SUPPORTED(PLL)
514 #if FE_SUPPORTED(STV0297) && FE_SUPPORTED(PLL)
/linux-2.6.39/drivers/video/omap2/dss/
DKconfig94 bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
98 Use DSI PLL to generate pixel clock. Currently only for DPI output.
99 DSI PLL can be used to generate higher and more precise pixel clocks.
/linux-2.6.39/Documentation/
DSM501.txt68 must be sourced from the same PLL, although they can then
71 attach if the PLL selection is different.
/linux-2.6.39/arch/blackfin/
DKconfig402 comment "Clock/PLL Setup"
428 bool "Bypass PLL"
437 If this is set the clock will be divided by 2, before it goes to the PLL.
452 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
453 PLL Frequency = (Crystal Frequency) * (this setting)
461 Core Frequency = (PLL frequency) / (this setting)
484 System Clock = (PLL frequency) / (this setting)
1213 The PLL and system clock (SCLK) continue to operate at a very low
1228 The PLL and system clock (SCLK), however, continue to operate in
1277 This option violates the PLL BYPASS recommendation in the Blackfin Processor
[all …]
/linux-2.6.39/arch/arm/mach-shmobile/include/mach/
Dhead-ap4evb.txt28 LIST "PLL"
Dhead-mackerel.txt28 LIST "PLL"
/linux-2.6.39/arch/blackfin/mach-bf533/
DKconfig29 int "PLL WAKEUP ERROR"
/linux-2.6.39/arch/arm/mach-s3c2440/
DKconfig63 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
70 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
/linux-2.6.39/Documentation/sound/alsa/soc/
Dclocking.txt13 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
/linux-2.6.39/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_200MHz_16MB21 # NOTE: Please change the master clock source from PLL-clock to Xin-clock
22 # and switch off PLL, before resetting the clock gear ratio.
Ddot.gdbinit_300MHz_32MB21 # NOTE: Please change the master clock source from PLL-clock to Xin-clock
22 # and switch off PLL, before resetting the clock gear ratio.
Ddot.gdbinit_400MHz_32MB21 # NOTE: Please change the master clock source from PLL-clock to Xin-clock
22 # and switch off PLL, before resetting the clock gear ratio.
/linux-2.6.39/arch/arm/mach-sa1100/
Dsleep.S48 @ delay 90us and set CPU PLL to lowest speed
/linux-2.6.39/drivers/media/dvb/frontends/
DKconfig183 tristate "Infineon TUA6100 PLL"
187 A DVB-S PLL chip.
538 comment "Digital terrestrial only tuners/PLL"
542 tristate "Generic I2C PLL based tuners"
546 This module drives a number of tuners based on PLL chips with a
/linux-2.6.39/arch/sh/include/mach-kfr2r09/mach/
Dpartner-jet-setup.txt30 LIST "The PLL and FLL values are updated here for the optimal"
/linux-2.6.39/arch/blackfin/mach-bf561/
DKconfig22 int "PLL Wakeup Interrupt"
/linux-2.6.39/drivers/staging/brcm80211/util/
Dsiutils.c118 si_clkctl_xtal(&sii->pub, XTAL | PLL, ON); in si_buscore_prep()
1280 if (what & PLL) in si_clkctl_xtal()
1287 if (what & PLL) in si_clkctl_xtal()
1297 if (what & PLL) { in si_clkctl_xtal()
1306 if (what & PLL) in si_clkctl_xtal()
/linux-2.6.39/Documentation/power/
Ds2ram.txt62 PLL's, and it just _hangs_. Using the regular VGA console and letting X
/linux-2.6.39/arch/arm/mach-s3c2410/
DKconfig62 Select the PLL table for the S3C2410
/linux-2.6.39/drivers/staging/brcm80211/include/
Dsiutils.h69 #define PLL 0x2 /* main chip pll */ macro
/linux-2.6.39/Documentation/video4linux/bttv/
DInsmod-options16 0: don't use PLL

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