Lines Matching refs:PLL

402 comment "Clock/PLL Setup"
428 	bool "Bypass PLL"
437 	  If this is set the clock will be divided by 2, before it goes to the PLL.
452 	  This controls the frequency of the on-chip PLL. This can be between 1 and 64.
453 	  PLL Frequency = (Crystal Frequency) * (this setting)
461 	  Core Frequency = (PLL frequency) / (this setting)
484 	  System Clock = (PLL frequency) / (this setting)
1213 	  The PLL and system clock (SCLK) continue to operate at a very low
1228 	  The PLL and system clock (SCLK), however, continue to operate in
1277 	  This option violates the PLL BYPASS recommendation in the Blackfin Processor
1279 	  the PLL may unlock.