Home
last modified time | relevance | path

Searched refs:NCR5380_read (Results 1 – 20 of 20) sorted by relevance

/linux-2.6.39/drivers/scsi/
DNCR5380.c336 r = NCR5380_read(reg); in NCR5380_poll_politely()
345 r = NCR5380_read(reg); in NCR5380_poll_politely()
424 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()
425 status = NCR5380_read(STATUS_REG); in NCR5380_print()
426 mr = NCR5380_read(MODE_REG); in NCR5380_print()
427 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()
428 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
466 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()
905 for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) { in NCR5380_init()
1177 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()
[all …]
Dsun3_NCR5380.c571 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()
572 status = NCR5380_read(STATUS_REG); in NCR5380_print()
573 mr = NCR5380_read(MODE_REG); in NCR5380_print()
574 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()
575 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
617 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()
1208 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1209 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()
1219 if((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | in NCR5380_dma_complete()
1222 printk("scsi%d: BASR %02x\n", HOSTNO, NCR5380_read(BUS_AND_STATUS_REG)); in NCR5380_dma_complete()
[all …]
Datari_NCR5380.c571 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()
572 status = NCR5380_read(STATUS_REG); in NCR5380_print()
573 mr = NCR5380_read(MODE_REG); in NCR5380_print()
574 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()
575 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
618 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()
1223 if ((NCR5380_read(BUS_AND_STATUS_REG) & in NCR5380_dma_complete()
1226 saved_data = NCR5380_read(INPUT_DATA_REG); in NCR5380_dma_complete()
1234 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1235 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()
[all …]
Dg_NCR5380.c585 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { in NCR5380_pread()
588 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pread()
592 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY); in NCR5380_pread()
598 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()
609 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()
618 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()
628 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) in NCR5380_pread()
636 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) in NCR5380_pread()
639 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) in NCR5380_pread()
643 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()
[all …]
Dmac_scsi.c358 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in mac_scsi_reset_boot()
366 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in mac_scsi_reset_boot()
466 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()
467 && !(NCR5380_read(STATUS_REG) & SR_REQ)) in macscsi_pread()
469 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()
470 && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) { in macscsi_pread()
558 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pwrite()
559 && (!(NCR5380_read(STATUS_REG) & SR_REQ) in macscsi_pwrite()
560 || (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))) in macscsi_pwrite()
562 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)) { in macscsi_pwrite()
Ddtc.c370 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()
380 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()
391 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pread()
395 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()
420 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pwrite()
431 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()
439 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pwrite()
443 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) in NCR5380_pwrite()
Dt128.h124 #define NCR5380_read(reg) readb(T128_address(reg)) macro
127 #define NCR5380_read(reg) \ macro
Ddtc.h73 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
76 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
Dpas16.h146 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro
149 #define NCR5380_read(reg) \ macro
Dg_NCR5380.h81 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro
106 #define NCR5380_read(reg) readb(iomem + NCR53C400_mem_base + (reg)) macro
Dsun3_scsi.c344 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in sun3_scsi_reset_boot()
354 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in sun3_scsi_reset_boot()
574 if(count && (NCR5380_read(BUS_AND_STATUS_REG) & in sun3scsi_dma_finish()
577 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG)); in sun3scsi_dma_finish()
Dpas16.c254 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in init_board()
331 if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */ in pas16_hw_detect()
334 if( NCR5380_read( MODE_REG ) != 0x00 ) in pas16_hw_detect()
Dmac_scsi.h65 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro
Dsun3_scsi_vme.c313 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in sun3_scsi_reset_boot()
323 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in sun3_scsi_reset_boot()
Ddmx3191d.c38 #define NCR5380_read(reg) inb(port + reg) macro
Datari_scsi.h49 #define NCR5380_read(reg) atari_scsi_reg_read( reg ) macro
Datari_scsi.c835 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG))); in atari_scsi_reset_boot()
843 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in atari_scsi_reset_boot()
Dsun3_scsi.h96 #define NCR5380_read(reg) sun3scsi_read(reg) macro
/linux-2.6.39/drivers/scsi/arm/
Doak.c30 #define NCR5380_read(reg) readb(_base + ((reg) << 2)) macro
Dcumana_1.c30 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro